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Searched refs:cache_mem_regs_write_mask (Results 1 – 7 of 7) sorted by relevance

/qemu/hw/cxl/
H A Dcxl-component-utils.c130 QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_regs_write_mask) != 4); in cxl_cache_mem_write_reg()
132 mask = cregs->cache_mem_regs_write_mask[offset / 4]; in cxl_cache_mem_write_reg()
/qemu/hw/pci-bridge/
H A Dcxl_downstream.c37 uint32_t *write_msk = dsp->cxl_cstate.crb.cache_mem_regs_write_mask; in latch_registers()
H A Dcxl_root_port.c101 uint32_t *write_msk = crp->cxl_cstate.crb.cache_mem_regs_write_mask; in latch_registers()
H A Dcxl_upstream.c89 uint32_t *write_msk = usp->cxl_cstate.crb.cache_mem_regs_write_mask; in latch_registers()
H A Dpci_expander_bridge.c290 uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask; in pxb_cxl_dev_reset()
/qemu/include/hw/cxl/
H A Dcxl_component.h225 uint32_t cache_mem_regs_write_mask[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; member
/qemu/hw/mem/
H A Dcxl_type3.c905 uint32_t *write_msk = ct3d->cxl_cstate.crb.cache_mem_regs_write_mask; in ct3d_reset()