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Searched refs:clock_set (Results 1 – 7 of 7) sorted by relevance

/qemu/include/hw/
H A Dclock.h188 bool clock_set(Clock *clk, uint64_t value);
192 return clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz)); in clock_set_hz()
197 return clock_set(clk, CLOCK_PERIOD_FROM_NS(ns)); in clock_set_ns()
223 if (clock_set(clk, value)) { in clock_update()
/qemu/hw/core/
H A Dclock.c55 bool clock_set(Clock *clk, uint64_t period) in clock_set() function
H A Dtrace-events28 clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', %"PRIu64"Hz->%"PRIu64"Hz"
/qemu/docs/devel/
H A Dclocks.rst282 Similarly to ``clock_set()``, ``clock_set_mul_div()`` returns ``true`` if
296 of 0. If this is not the desired behaviour, ``clock_set()``,
435 ``clock_set[_ns|_hz]()`` (with the same arguments) then
518 device state. The functions ``clock_set[_ns|_hz]()`` can be used during the
525 suitable ``needed`` function, and use ``clock_set()`` in a
/qemu/hw/misc/
H A Dzynq_slcr.c281 clock_set(s->uart0_ref_clk, in zynq_slcr_compute_clocks_internal()
283 clock_set(s->uart1_ref_clk, in zynq_slcr_compute_clocks_internal()
H A Dbcm2835_cprman.c683 clock_set(s->gnd, 0); in cprman_init()
H A Dstm32l4x5_rcc.c65 clk_changed |= clock_set(mux->out, clock_get(current_source)); in clock_mux_update()