/qemu/target/arm/ |
H A D | debug_helper.c | 151 if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) { in arm_generate_debug_exceptions() 176 uint64_t bcr = env->cp15.dbgbcr[lbn]; in linked_bp_matches() 194 bcr = env->cp15.dbgbcr[lbn]; in linked_bp_matches() 274 cr = env->cp15.dbgwcr[n]; in bp_wp_matches() 289 cr = env->cp15.dbgbcr[n]; in bp_wp_matches() 551 vaddr wvr = env->cp15.dbgwvr[n]; in hw_watchpoint_update() 552 uint64_t wcr = env->cp15.dbgwcr[n]; in hw_watchpoint_update() 656 uint64_t bvr = env->cp15.dbgbvr[n]; in hw_breakpoint_update() 657 uint64_t bcr = env->cp15.dbgbcr[n]; in hw_breakpoint_update() 904 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); in oslar_write() [all …]
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H A D | helper.c | 1280 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); in pmu_update_irq() 1381 env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; in pmccntr_op_finish() 1488 env->cp15.c15_ccnt = 0; in pmcr_write() 1560 ret = env->cp15.c15_ccnt; in pmccntr_read() 1581 env->cp15.c15_ccnt = value; in pmccntr_write() 1606 env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | in pmccfiltr_write_a32() 1955 env->cp15.scr_el3 = value; in scr_write() 7067 env->cp15.disr_el1 = val; in disr_write() 7478 env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask); in gpccr_write() 11237 addr += env->cp15.hvbar; in arm_cpu_do_interrupt_aarch32_hyp() [all …]
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H A D | cpu.c | 267 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold() 271 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold() 278 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold() 313 env->cp15.mdscr_el1 |= 1 << 12; in arm_cpu_reset_hold() 328 env->pc = env->cp15.rvbar; in arm_cpu_reset_hold() 333 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold() 335 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold() 349 env->cp15.c15_cpar = 3; in arm_cpu_reset_hold() 351 env->cp15.c15_cpar = 1; in arm_cpu_reset_hold() 641 env->cp15.scr_el3 |= SCR_NS; in arm_emulate_firmware_reset() [all …]
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H A D | ptw.c | 197 return env->cp15.vttbr_el2; in regime_ttbr() 200 return env->cp15.vsttbr_el2; in regime_ttbr() 293 uint64_t gpccr = env->cp15.gpccr_el3; in granule_protection_check() 366 tableaddr = env->cp15.gptbr_el3 << 12; in granule_protection_check() 1023 dacr = env->cp15.dacr_ns; in get_phys_addr_v5() 1025 dacr = env->cp15.dacr_s; in get_phys_addr_v5() 1163 dacr = env->cp15.dacr_ns; in get_phys_addr_v6() 1165 dacr = env->cp15.dacr_s; in get_phys_addr_v6() 2214 base = env->cp15.c6_region[n]; in get_phys_addr_pmsav5() 2232 mask = env->cp15.pmsav5_insn_ap; in get_phys_addr_pmsav5() [all …]
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H A D | internals.h | 438 uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled() 940 return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; in regime_sctlr() 957 return env->cp15.vtcr_el2; in regime_tcr() 968 uint64_t v = env->cp15.vstcr_el2 & ~VTCR_SHARED_FIELD_MASK; in regime_tcr() 969 v |= env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK; in regime_tcr() 972 return env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr() 1338 && !(env->cp15.scr_el3 & SCR_ATA)) { in allocation_tag_access_enabled() 1694 return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; in arm_mdcr_el2_eff() 1719 (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN)); in arm_fgt_active()
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H A D | cpu.h | 526 } cp15; member 2491 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); in arm_is_el2_enabled_secstate() 2560 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { in arm_el_is_aa64() 2561 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); in arm_el_is_aa64() 2569 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); in arm_el_is_aa64() 2586 !(env->cp15.scr_el3 & SCR_NS)); in access_secure_reg() 2593 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2598 (_env)->cp15._regname##_s = (_val); \ 2600 (_env)->cp15._regname##_ns = (_val); \ 2953 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; in arm_sctlr_b()
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H A D | arch_dump.c | 439 info->d_endian = (env->cp15.sctlr_el[1] & SCTLR_EE) != 0 in cpu_get_dump_info()
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/qemu/bsd-user/arm/ |
H A D | target_arch_cpu.c | 26 env->cp15.tpidrurw_s = newtls; in target_cpu_set_tls() 27 env->cp15.tpidruro_s = newtls; in target_cpu_set_tls() 31 env->cp15.tpidr_el[0] = newtls; in target_cpu_set_tls() 32 env->cp15.tpidrro_el[0] = newtls; in target_cpu_set_tls() 38 return env->cp15.tpidruro_s; in target_cpu_get_tls() 40 return env->cp15.tpidrro_el[0]; in target_cpu_get_tls()
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/qemu/target/arm/hvf/ |
H A D | hvf.c | 1214 val = env->cp15.c9_pmcr; in hvf_sysreg_read() 1218 val = env->cp15.c15_ccnt; in hvf_sysreg_read() 1225 val = env->cp15.c9_pmovsr; in hvf_sysreg_read() 1228 val = env->cp15.c9_pmselr; in hvf_sysreg_read() 1248 val = env->cp15.oslsr_el1; in hvf_sysreg_read() 1388 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); in pmu_update_irq() 1503 env->cp15.c15_ccnt = val; in hvf_sysreg_write() 2230 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug() 2234 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug() 2240 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug() [all …]
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/qemu/linux-user/arm/ |
H A D | target_cpu.h | 60 env->cp15.tpidruro_s = newtls; in cpu_set_tls() 62 env->cp15.tpidrro_el[0] = newtls; in cpu_set_tls() 69 return env->cp15.tpidruro_s; in cpu_get_tls() 71 return env->cp15.tpidrro_el[0]; in cpu_get_tls()
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H A D | cpu_loop.c | 532 env->cp15.sctlr_el[1] |= SCTLR_E0E; in target_cpu_copy_regs() 534 env->cp15.sctlr_el[1] |= SCTLR_B; in target_cpu_copy_regs()
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H A D | signal.c | 207 if (env->cp15.sctlr_el[1] & SCTLR_E0E) { in setup_return()
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/qemu/linux-user/aarch64/ |
H A D | target_prctl.h | 195 env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); in do_prctl_set_tagged_addr_ctrl() 202 env->cp15.gcr_el1 = in do_prctl_set_tagged_addr_ctrl() 203 deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT); in do_prctl_set_tagged_addr_ctrl() 220 ret |= extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHIFT; in do_prctl_get_tagged_addr_ctrl() 221 ret = deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1); in do_prctl_get_tagged_addr_ctrl()
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H A D | cpu_loop.c | 175 if (unlikely(env->cp15.tfsr_el[0])) { in cpu_loop() 176 env->cp15.tfsr_el[0] = 0; in cpu_loop() 208 env->cp15.sctlr_el[1] |= SCTLR_E0E; in target_cpu_copy_regs() 210 env->cp15.sctlr_el[i] |= SCTLR_EE; in target_cpu_copy_regs()
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H A D | target_cpu.h | 41 env->cp15.tpidr_el[0] = newtls; in cpu_set_tls() 43 env->cp15.tpidr2_el0 = 0; in cpu_set_tls()
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/qemu/target/arm/tcg/ |
H A D | op_helper.c | 305 if (env->cp15.hstr_el2 & HSTR_TJDBX) { in HELPER() 344 if (!(env->cp15.sctlr_el[target_el] & mask)) { in check_wfx_trap() 363 if (env->cp15.scr_el3 & mask) { in check_wfx_trap() 750 if (env->cp15.hstr_el2 & mask) { in HELPER() 770 trapword = env->cp15.fgt_exec[idx]; in HELPER() 773 trapword = env->cp15.fgt_read[idx]; in HELPER() 776 trapword = env->cp15.fgt_write[idx]; in HELPER() 951 undef = !(env->cp15.scr_el3 & SCR_HCE); in HELPER() 953 undef = env->cp15.hcr_el2 & HCR_HCD; in HELPER() 976 bool smd_flag = env->cp15.scr_el3 & SCR_SMD; in HELPER() [all …]
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H A D | tlb_helper.c | 139 ret = (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el != 3; in report_as_gpc_exception() 206 env->cp15.mfar_el3 = fi->paddr; in arm_deliver_fault() 211 env->cp15.mfar_el3 |= R_MFAR_NS_MASK; in arm_deliver_fault() 214 env->cp15.mfar_el3 |= R_MFAR_NSE_MASK; in arm_deliver_fault() 217 env->cp15.mfar_el3 |= R_MFAR_NSE_MASK | R_MFAR_NS_MASK; in arm_deliver_fault() 236 env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; in arm_deliver_fault() 238 env->cp15.hpfar_el2 |= HPFAR_NS; in arm_deliver_fault()
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H A D | hflags.c | 25 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) : in fgt_svc() 26 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); in fgt_svc() 171 if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && in rebuild_hflags_a32() 195 || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) in rebuild_hflags_a32() 313 if (env->cp15.hcr_el2 & HCR_TGE) { in rebuild_hflags_a64() 328 if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { in rebuild_hflags_a64() 351 if (env->cp15.sctlr_el[2] & SCTLR_EE) { in rebuild_hflags_a64()
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H A D | mte_helper.c | 231 uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); in HELPER() 232 int rrnd = extract32(env->cp15.gcr_el1, 16, 1); in HELPER() 233 int start = extract32(env->cp15.rgsr_el1, 0, 4); in HELPER() 234 int seed = extract32(env->cp15.rgsr_el1, 8, 16); in HELPER() 272 env->cp15.rgsr_el1 = rtag | (seed << 8); in HELPER() 281 uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); in HELPER() 607 env->cp15.tfsr_el[el] |= 1 << select; in mte_async_check_fail() 630 sctlr = env->cp15.sctlr_el[reg_el]; in mte_check_fail()
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H A D | cpu32.c | 171 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), in arm1026_initfn() 362 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 365 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 368 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
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H A D | helper-a64.c | 800 if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) { in HELPER() 1002 return env->cp15.sctlr_el[1] & SCTLR_MSCEN; in mops_enabled() 1004 return env->cp15.sctlr_el[2] & SCTLR_MSCEN; in mops_enabled()
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H A D | pauth_helper.c | 479 if (!(env->cp15.scr_el3 & SCR_API)) { in pauth_check_trap()
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/qemu/hw/arm/ |
H A D | boot.c | 701 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; in do_cpu_reset() 703 env->cp15.sctlr_el[i] &= ~SCTLR_EE; in do_cpu_reset() 708 env->cp15.sctlr_el[1] |= SCTLR_E0E; in do_cpu_reset() 710 env->cp15.sctlr_el[i] |= SCTLR_EE; in do_cpu_reset() 715 env->cp15.sctlr_el[1] |= SCTLR_B; in do_cpu_reset()
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H A D | pxa2xx.c | 299 s->cpu->env.cp15.sctlr_ns = 0; in pxa2xx_pwrmode_write() 300 s->cpu->env.cp15.cpacr_el1 = 0; in pxa2xx_pwrmode_write() 301 s->cpu->env.cp15.ttbr0_el[1] = 0; in pxa2xx_pwrmode_write() 302 s->cpu->env.cp15.dacr_ns = 0; in pxa2xx_pwrmode_write()
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/qemu/hw/intc/ |
H A D | arm_gicv3_cpuif.c | 816 bool nmi = env->cp15.sctlr_el[el] & SCTLR_NMI && lr & ICH_LR_EL2_NMI; in icv_iar_read() 1114 (env->cp15.scr_el3 & SCR_FIQ)) { in icc_pmr_read() 1143 (env->cp15.scr_el3 & SCR_FIQ)) { in icc_pmr_write() 1302 if (cs->hppi.nmi && env->cp15.sctlr_el[el] & SCTLR_NMI) { in icc_iar1_read() 1920 route_fiq_to_el3 = env->cp15.scr_el3 & SCR_FIQ; in icc_dir_write() 1921 route_irq_to_el3 = env->cp15.scr_el3 & SCR_IRQ; in icc_dir_write() 1980 !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { in icc_rpr_read() 2282 if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) { in gicv3_irqfiq_access() 2348 if (env->cp15.scr_el3 & SCR_FIQ) { in gicv3_fiq_access() 2387 if (env->cp15.scr_el3 & SCR_IRQ) { in gicv3_irq_access()
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