Searched refs:cpacr_el1 (Results 1 – 5 of 5) sorted by relevance
| /qemu/tests/tcg/aarch64/system/ |
| H A D | boot.S | 186 mrs x0, cpacr_el1
189 msr cpacr_el1, x0
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| /qemu/target/arm/ |
| H A D | cpu.c | 267 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
271 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
278 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
333 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
335 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
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| H A D | helper.c | 797 value = (value & ~mask) | (env->cp15.cpacr_el1 & mask); in cpacr_write()
800 env->cp15.cpacr_el1 = value; in cpacr_write()
809 uint64_t value = env->cp15.cpacr_el1; in cpacr_read()
889 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
7127 switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { in sve_exception_el()
7176 switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) { in sme_exception_el()
12458 int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); in fp_exception_el()
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| H A D | cpu.h | 288 uint64_t cpacr_el1; /* Architectural feature access control register */ member
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| /qemu/hw/arm/ |
| H A D | pxa2xx.c | 300 s->cpu->env.cp15.cpacr_el1 = 0; in pxa2xx_pwrmode_write()
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