/qemu/target/openrisc/ |
H A D | translate.c | 422 gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_add() 429 gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_addc() 436 gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_sub() 443 tcg_gen_and_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_and() 450 tcg_gen_or_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_or() 457 tcg_gen_xor_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_xor() 544 gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_mul() 551 gen_mulu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_mulu() 558 gen_div(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_div() 565 gen_divu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_divu() [all …]
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/qemu/target/cris/ |
H A D | translate.c | 1237 cpu_R[dc->op2], cpu_R[dc->op2], c, 4); in dec_addq() 1261 cpu_R[dc->op2], cpu_R[dc->op2], c, 4); in dec_subq() 1276 cpu_R[dc->op2], cpu_R[dc->op2], c, 4); in dec_cmpq() 1320 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); in dec_btstq() 1334 cpu_R[dc->op2], cpu_R[dc->op2], 4); in dec_asrq() 1348 cpu_R[dc->op2], cpu_R[dc->op2], 4); in dec_lslq() 1361 cpu_R[dc->op2], cpu_R[dc->op2], 4); in dec_lsrq() 1528 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); in dec_dstep_r() 1582 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); in dec_abs_r() 1611 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); in dec_addc_r() [all …]
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H A D | translate_v10.c.inc | 146 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size); 176 tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len); 448 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); 476 tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0); 691 cpu_R[dc->dst], cpu_R[dc->src], 4); 698 cpu_R[dc->dst], cpu_R[dc->src], 4); 858 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size); 877 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4); 901 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4); 924 tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2); [all …]
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/qemu/target/microblaze/ |
H A D | translate.c | 49 static TCGv_i32 cpu_R[32]; variable 179 return cpu_R[reg]; in reg_for_read() 194 return cpu_R[reg]; in reg_for_write() 632 tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]); in DO_TYPEA() 635 tcg_gen_extu_i32_tl(ret, cpu_R[ra]); in DO_TYPEA() 637 tcg_gen_extu_i32_tl(ret, cpu_R[rb]); in DO_TYPEA() 655 tcg_gen_addi_i32(tmp, cpu_R[ra], imm); in compute_ldst_addr_typeb() 675 tcg_gen_extu_i32_tl(ret, cpu_R[rb]); in compute_ldst_addr_ea() 681 tcg_gen_concat_i32_i64(ret, cpu_R[rb], cpu_R[ra]); in compute_ldst_addr_ea() 683 tcg_gen_extu_i32_tl(ret, cpu_R[ra]); in compute_ldst_addr_ea() [all …]
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/qemu/target/arm/tcg/ |
H A D | translate.c | 49 static TCGv_i32 cpu_R[16]; variable 317 tcg_gen_mov_i32(cpu_R[reg], var); in store_reg() 1498 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); in disas_iwmmxt_insn() 2508 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1); in disas_dsp_insn() 2510 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); in disas_dsp_insn() 2892 tcg_gen_mov_i32(cpu_R[15], pc); in store_pc_exc_ret() 3361 tcg_gen_mov_i32(cpu_R[rd], t0); in gen_store_exclusive() 4146 fn(cpu_R[a->rda], cpu_R[a->rda], a->shim); in do_mve_sh_ri() 4197 fn(cpu_R[a->rda], tcg_env, cpu_R[a->rda], cpu_R[a->rm]); in do_mve_sh_rr() 6835 tcg_gen_addi_i32(cpu_R[14], cpu_R[14], -1); in trans_LE() [all …]
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/qemu/target/xtensa/ |
H A D | translate.c | 80 static TCGv_i32 cpu_R[16]; variable 159 cpu_R[i] = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init() 249 (void *)"AR 16x32", (void *)cpu_R); in xtensa_get_regfile_by_name() 251 (void *)"AR 32x32", (void *)cpu_R); in xtensa_get_regfile_by_name() 253 (void *)"AR 64x32", (void *)cpu_R); in xtensa_get_regfile_by_name() 399 tcg_gen_movi_i32(cpu_R[callinc << 2], in gen_callw_slot() 1456 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); in translate_call0() 1472 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); in translate_callx0() 2000 gen_jump(dc, cpu_R[0]); in translate_ret() 2026 tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30); in translate_retw() [all …]
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