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Searched refs:cr (Results 1 – 25 of 108) sorted by relevance

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/qemu/target/hppa/
H A Dgdbstub.c115 val = env->cr[24]; in hppa_cpu_gdb_read_register()
118 val = env->cr[25]; in hppa_cpu_gdb_read_register()
121 val = env->cr[26]; in hppa_cpu_gdb_read_register()
124 val = env->cr[27]; in hppa_cpu_gdb_read_register()
127 val = env->cr[28]; in hppa_cpu_gdb_read_register()
130 val = env->cr[29]; in hppa_cpu_gdb_read_register()
133 val = env->cr[30]; in hppa_cpu_gdb_read_register()
245 env->cr[24] = val; in hppa_cpu_gdb_write_register()
248 env->cr[25] = val; in hppa_cpu_gdb_write_register()
251 env->cr[26] = val; in hppa_cpu_gdb_write_register()
[all …]
H A Dint_helper.c31 if (cpu->env.cr[CR_EIRR]) { in eval_interrupt()
48 return cpu->env.cr[CR_EIRR]; in io_eir_read()
65 env->cr[CR_EIRR] |= 1ull << le_bit; in io_eir_write()
86 env->cr[CR_EIRR] &= ~val; in HELPER()
101 env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); in hppa_cpu_do_interrupt()
114 env->cr[CR_IIASQ] = in hppa_cpu_do_interrupt()
119 env->cr[CR_IIASQ] = 0; in hppa_cpu_do_interrupt()
124 env->cr[CR_IIAOQ] = env->iaoq_f; in hppa_cpu_do_interrupt()
127 env->cr[CR_IIAOQ] = (uint32_t)env->iaoq_f; in hppa_cpu_do_interrupt()
173 env->cr[CR_IIR] = 0; in hppa_cpu_do_interrupt()
[all …]
H A Dsys_helper.c48 cpu->env.cr[CR_IT] = timeout; in HELPER()
84 cpu_hppa_put_psw(env, env->cr[CR_IPSW]); in HELPER()
93 env->iaoq_f = env->cr[CR_IIAOQ]; in HELPER()
95 env->iasq_f = (env->cr[CR_IIASQ] << 32) & ~(env->iaoq_f & mask); in HELPER()
H A Dmem_helper.c174 r = match_prot_id_1(access_id, env->cr[i]); in match_prot_id32()
187 r = match_prot_id_1(access_id, env->cr[i]); in match_prot_id64()
191 r = match_prot_id_1(access_id, env->cr[i] >> 32); in match_prot_id64()
362 env->cr[CR_IOR] = (uint32_t)addr; in hppa_set_ior_and_isr()
363 env->cr[CR_ISR] = addr >> 32; in hppa_set_ior_and_isr()
371 env->cr[CR_ISR] &= 0x3fffffff; in hppa_set_ior_and_isr()
382 env->cr[CR_IOR] |= b << 62; in hppa_set_ior_and_isr()
570 vaddr va_b = deposit64(env->cr[CR_IOR], 32, 32, env->cr[CR_ISR]); in HELPER()
576 vaddr va_b = deposit64(env->cr[CR_IIAOQ], 32, 32, env->cr[CR_IIASQ]); in HELPER()
/qemu/hw/timer/
H A Dimx_epit.c70 if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { in imx_epit_update_int()
94 s->cr = 0; in imx_epit_reset()
125 reg_value = s->cr; in imx_epit_read()
226 uint32_t oldcr = s->cr; in imx_epit_write_cr()
228 s->cr = value & 0x03ffffff; in imx_epit_write_cr()
230 if (s->cr & CR_SWR) { in imx_epit_write_cr()
265 if (freq && (s->cr & CR_EN)) { in imx_epit_write_cr()
300 if (s->cr & CR_RLD) { in imx_epit_write_lr()
305 } else if (s->cr & CR_IOVW) { in imx_epit_write_lr()
363 assert(s->cr & CR_EN); in imx_epit_cmp()
[all …]
H A Dimx_gpt.c67 VMSTATE_UINT32(cr, IMXGPTState),
188 if (!(s->cr & GPT_CR_EN)) { in imx_gpt_compute_next_timeout()
270 reg_value = s->cr; in imx_gpt_read()
341 s->cr = 0; in imx_gpt_reset_common()
363 if (s->freq && (s->cr & GPT_CR_EN)) { in imx_gpt_reset_common()
392 oldreg = s->cr; in imx_gpt_write()
393 s->cr = value & ~0x7c14; in imx_gpt_write()
402 if ((oldreg ^ s->cr) & GPT_CR_EN) { in imx_gpt_write()
403 if (s->cr & GPT_CR_EN) { in imx_gpt_write()
446 if (!(s->cr & GPT_CR_FRR)) { in imx_gpt_write()
[all …]
/qemu/hw/display/
H A Dvga.c398 val = s->cr[s->cr_index]; in vga_ioport_read()
521 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) | in vga_ioport_write()
527 s->cr[s->cr_index] = val; in vga_ioport_write()
652 s->cr[VGA_CRTC_H_DISP] = in vbe_update_vgaregs()
656 s->cr[VGA_CRTC_V_DISP_END] = h; in vbe_update_vgaregs()
657 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) | in vbe_update_vgaregs()
661 s->cr[VGA_CRTC_OVERFLOW] |= 0x10; in vbe_update_vgaregs()
662 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40; in vbe_update_vgaregs()
1507 if (s->cr[VGA_CRTC_MODE] & 1) { in vga_draw_graphic()
1664 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE], in vga_draw_graphic()
[all …]
H A Dpl110.c66 uint32_t cr; member
92 VMSTATE_UINT32(cr, PL110State),
210 return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR); in pl110_enabled()
227 if (s->cr & PL110_CR_BGR) in pl110_update_display()
260 if (s->cr & PL110_CR_BEBO) { in pl110_update_display()
262 } else if (s->cr & PL110_CR_BEPO) { in pl110_update_display()
416 return s->cr; in pl110_read()
423 return s->cr; in pl110_read()
492 s->cr = val; in pl110_write()
/qemu/target/i386/
H A Dhelper.c37 if ((env->cr[4] & CR4_OSXSAVE_MASK) in cpu_sync_avx_hflag()
58 if ((env->cr[4] & CR4_OSXSAVE_MASK) in cpu_sync_bndcs_hflags()
142 if (!(env->cr[4] & CR4_PAE_MASK)) in cpu_x86_update_cr0()
154 env->cr[0] = new_cr0 | CR0_ET_MASK; in cpu_x86_update_cr0()
157 pe_state = (env->cr[0] & CR0_PE_MASK); in cpu_x86_update_cr0()
170 env->cr[3] = new_cr3; in cpu_x86_update_cr3()
171 if (env->cr[0] & CR0_PG_MASK) { in cpu_x86_update_cr3()
185 if ((new_cr4 ^ env->cr[4]) & in cpu_x86_update_cr4()
226 env->cr[4] = new_cr4; in cpu_x86_update_cr4()
248 if (!(env->cr[0] & CR0_PG_MASK)) { in x86_cpu_get_phys_page_attrs_debug()
[all …]
H A Dmonitor.c39 if (env->cr[4] & CR4_LA57_MASK) { in addr_canonical()
77 pgd = env->cr[3] & ~0xfff; in tlb_info_32()
106 pdp_addr = env->cr[3] & ~0x1f; in tlb_info_pae32()
228 if (!(env->cr[0] & CR0_PG_MASK)) { in hmp_info_tlb()
232 if (env->cr[4] & CR4_PAE_MASK) { in hmp_info_tlb()
235 if (env->cr[4] & CR4_LA57_MASK) { in hmp_info_tlb()
282 pgd = env->cr[3] & ~0xfff; in mem_info_32()
324 pdp_addr = env->cr[3] & ~0x1f; in mem_info_pae32()
556 if (!(env->cr[0] & CR0_PG_MASK)) { in hmp_info_mem()
560 if (env->cr[4] & CR4_PAE_MASK) { in hmp_info_mem()
[all …]
H A Darch_memory_mapping.c282 if (env->cr[4] & CR4_PAE_MASK) { in x86_cpu_get_memory_mapping()
285 if (env->cr[4] & CR4_LA57_MASK) { in x86_cpu_get_memory_mapping()
288 pml5e_addr = (env->cr[3] & PLM4_ADDR_MASK) & a20_mask; in x86_cpu_get_memory_mapping()
293 pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & a20_mask; in x86_cpu_get_memory_mapping()
302 pdpe_addr = (env->cr[3] & ~0x1f) & a20_mask; in x86_cpu_get_memory_mapping()
309 pde_addr = (env->cr[3] & ~0xfff) & a20_mask; in x86_cpu_get_memory_mapping()
310 pse = !!(env->cr[4] & CR4_PSE_MASK); in x86_cpu_get_memory_mapping()
H A Darch_dump.c260 uint64_t cr[5]; member
319 s->cr[0] = env->cr[0]; in qemu_get_cpustate()
320 s->cr[1] = env->cr[1]; in qemu_get_cpustate()
321 s->cr[2] = env->cr[2]; in qemu_get_cpustate()
322 s->cr[3] = env->cr[3]; in qemu_get_cpustate()
323 s->cr[4] = env->cr[4]; in qemu_get_cpustate()
/qemu/hw/i2c/
H A Dmpc_i2c.c82 uint8_t cr; member
90 return s->cr & CCR_MEN; in mpc_i2c_is_enabled()
95 return s->cr & CCR_MSTA; in mpc_i2c_is_master()
100 return s->cr & CCR_MTX; in mpc_i2c_direction_is_tx()
110 return s->cr & CCR_MIEN; in mpc_i2c_irq_is_enabled()
120 i2c->cr = 0x00; in mpc_i2c_reset()
206 value = s->cr; in mpc_i2c_read()
252 s->cr = value & CCR_MASK; in mpc_i2c_write()
266 if (s->cr & CCR_RSTA) { in mpc_i2c_write()
270 s->cr &= ~CCR_RSTA; in mpc_i2c_write()
[all …]
/qemu/hw/net/
H A Dsunhme.c574 cr = sunhme_get_tx_ring_nr(s); in sunhme_transmit()
634 cr++; in sunhme_transmit()
635 if (cr >= nr) { in sunhme_transmit()
636 cr = 0; in sunhme_transmit()
638 sunhme_set_tx_ring_nr(s, cr); in sunhme_transmit()
725 int nr, cr, len, rxoffset, csum_offset; in sunhme_receive() local
777 cr = sunhme_get_rx_ring_nr(s); in sunhme_receive()
825 cr++; in sunhme_receive()
826 if (cr >= nr) { in sunhme_receive()
827 cr = 0; in sunhme_receive()
[all …]
/qemu/hw/misc/
H A Dstm32l4x5_rcc.c407 s->cr = (s->cr & ~R_CSR_MSISRANGE_MASK) | in rcc_update_msi()
427 s->cr = (s->cr & ~R_CR_PLLSAI2RDY_MASK) | in rcc_update_cr_register()
436 s->cr = (s->cr & ~R_CR_PLLSAI1RDY_MASK) | in rcc_update_cr_register()
449 s->cr = (s->cr & ~R_CR_PLLRDY_MASK) | in rcc_update_cr_register()
455 s->cr |= R_CR_PLLON_MASK; in rcc_update_cr_register()
469 s->cr = (s->cr & ~R_CR_HSERDY_MASK) | in rcc_update_cr_register()
480 s->cr |= R_CR_HSEON_MASK; in rcc_update_cr_register()
913 s->cr = 0x00000063; in stm32l4x5_rcc_reset_hold()
957 retvalue = s->cr; in stm32l4x5_rcc_read()
1068 previous_value = s->cr; in stm32l4x5_rcc_write()
[all …]
/qemu/hw/char/
H A Dpl011.c201 r = s->cr; in pl011_read()
267 return !!(s->cr & CR_LBE); in pl011_loopback_enabled()
272 uint32_t cr, fr, il; in pl011_loopback_mdmctrl() local
291 cr = s->cr; in pl011_loopback_mdmctrl()
294 fr |= (cr & CR_OUT2) ? PL011_FLAG_RI : 0; in pl011_loopback_mdmctrl()
295 fr |= (cr & CR_OUT1) ? PL011_FLAG_DCD : 0; in pl011_loopback_mdmctrl()
296 fr |= (cr & CR_RTS) ? PL011_FLAG_CTS : 0; in pl011_loopback_mdmctrl()
297 fr |= (cr & CR_DTR) ? PL011_FLAG_DSR : 0; in pl011_loopback_mdmctrl()
400 s->cr = value; in pl011_write()
547 VMSTATE_UINT32(cr, PL011State),
[all …]
/qemu/target/ppc/
H A Dcpu.c71 void ppc_set_cr(CPUPPCState *env, uint64_t cr) in ppc_set_cr() argument
74 env->crf[i] = cr & 0xf; in ppc_set_cr()
75 cr >>= 4; in ppc_set_cr()
81 uint64_t cr = 0; in ppc_get_cr() local
83 cr |= (env->crf[i] & 0xf) << (4 * (7 - i)); in ppc_get_cr()
85 return cr; in ppc_get_cr()
H A Dint_helper.c2395 return cr; in helper_bcdadd()
2445 return cr; in helper_bcdcfn()
2479 return cr; in helper_bcdctn()
2523 return cr; in helper_bcdcfz()
2566 return cr; in helper_bcdctz()
2588 int cr; in helper_bcdcfsq() local
2640 return cr; in helper_bcdcfsq()
2646 int cr; in helper_bcdctsq() local
2722 int cr; in helper_bcds() local
2758 int cr; in helper_bcdus() local
[all …]
H A Dgdbstub.c132 uint32_t cr = ppc_get_cr(env); in ppc_cpu_gdb_read_register() local
133 gdb_get_reg32(buf, cr); in ppc_cpu_gdb_read_register()
182 uint32_t cr = ppc_get_cr(env); in ppc_cpu_gdb_read_register_apple() local
183 gdb_get_reg32(buf, cr); in ppc_cpu_gdb_read_register_apple()
230 uint32_t cr = ldl_p(mem_buf); in ppc_cpu_gdb_write_register() local
231 ppc_set_cr(env, cr); in ppc_cpu_gdb_write_register()
276 uint32_t cr = ldl_p(mem_buf); in ppc_cpu_gdb_write_register_apple() local
277 ppc_set_cr(env, cr); in ppc_cpu_gdb_write_register_apple()
/qemu/target/i386/tcg/
H A Dmisc_helper.c68 if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) { in helper_rdtsc()
80 if (((env->cr[4] & CR4_PCE_MASK) == 0 ) && in helper_rdpmc()
110 if ((env->cr[4] & CR4_PKE_MASK) == 0) { in helper_rdpkru()
124 if ((env->cr[4] & CR4_PKE_MASK) == 0) { in helper_wrpkru()
/qemu/hw/input/
H A Dpl050.c34 VMSTATE_UINT32(cr, PL050State),
56 int level = (s->pending && (s->cr & 0x10) != 0) in pl050_update_irq()
57 || (s->cr & 0x08) != 0; in pl050_update_irq()
81 return s->cr; in pl050_read()
125 s->cr = value; in pl050_write()
/qemu/tests/tcg/ppc64/
H A Dbcdsub.c28 int cr = 0; \
46 : "=r" (cr), "=r" (th), "=r" (tl) \
53 assert((cr >> 4) == CR6); \
/qemu/hw/intc/
H A Dppc-uic.c54 uint32_t ir, cr; in ppcuic_trigger_irq() local
59 cr = uic->uicsr & uic->uicer & uic->uiccr; in ppcuic_trigger_irq()
64 uic->uicsr & uic->uicer, ir, cr); in ppcuic_trigger_irq()
73 if (cr != 0x0000000) { in ppcuic_trigger_irq()
88 if (cr & (1 << i)) { in ppcuic_trigger_irq()
/qemu/hw/audio/
H A Dac97.c115 uint8_t cr; /* rw 0 */ member
216 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) { in update_sr()
274 r->cr = r->cr & CR_DONT_CLEAR_MASK; in reset_bm_regs()
687 val = r->cr; in nabm_readb()
758 val = r->picb | (r->piv << 16) | (r->cr << 24); in nabm_readl()
760 val, r->picb, r->piv, r->cr); in nabm_readl()
791 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) { in nabm_writeb()
807 r->cr = val & CR_VALID_MASK; in nabm_writeb()
808 if (!(r->cr & CR_RPBM)) { in nabm_writeb()
1006 if (r->cr & CR_RPBM) { in transfer_audio()
[all …]
/qemu/hw/pci-host/
H A Ddesignware.c205 val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) / in designware_pcie_root_config_read()
273 const bool enabled = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE; in designware_pcie_update_viewport()
277 if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) { in designware_pcie_update_viewport()
373 viewport->cr[0] = val; in designware_pcie_root_config_write()
376 viewport->cr[1] = val; in designware_pcie_root_config_write()
435 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; in designware_pcie_root_realize()
459 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; in designware_pcie_root_realize()
501 viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE; in designware_pcie_root_realize()
566 VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2),

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