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Searched refs:dma (Results 1 – 25 of 78) sorted by relevance

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/qemu/hw/dma/
H A Dsoc_dma.c89 struct dma_s *dma = (struct dma_s *) ch->dma; in soc_dma_ch_schedule() local
114 lo = dma->memmap; in soc_dma_lookup()
129 struct dma_s *dma = (struct dma_s *) ch->dma; in soc_dma_ch_update_type() local
133 while (entry < dma->memmap + dma->memmap_size && in soc_dma_ch_update_type()
207 struct dma_s *dma = (struct dma_s *) ch->dma; in soc_dma_set_request() local
265 dma->memmap = g_realloc(dma->memmap, sizeof(*entry) * in soc_dma_port_add_fifo()
284 while (entry < dma->memmap + dma->memmap_size && in soc_dma_port_add_fifo()
297 (uint8_t *) (dma->memmap + dma->memmap_size ++) - in soc_dma_port_add_fifo()
315 dma->memmap = g_realloc(dma->memmap, sizeof(*entry) * in soc_dma_port_add_mem()
344 while (entry < dma->memmap + dma->memmap_size && in soc_dma_port_add_mem()
[all …]
H A Domap_dma.c93 struct soc_dma_ch_s *dma; member
105 struct soc_dma_s *dma; member
505 struct omap_dma_s *s = dma->dma->opaque;
594 if (dma->update) {
658 if (dma->update) {
1655 s->dma->opaque = s;
1664 s->ch[i].dma = &s->dma->ch[i];
1678 return s->dma;
2096 s->dma->opaque = s;
2098 s->ch[i].dma = &s->dma->ch[i];
[all …]
H A Dxilinx_axidma.c104 struct XilinxAXIDMA *dma; member
121 struct XilinxAXIDMA *dma; member
301 address_space_read(&s->dma->as, addr, in stream_process_mem2s()
396 struct Stream *s = &cs->dma->streams[1]; in xilinx_axidma_control_stream_push()
413 struct Stream *s = &ds->dma->streams[1]; in xilinx_axidma_data_stream_can_push()
416 ds->dma->notify = notify; in xilinx_axidma_data_stream_can_push()
417 ds->dma->notify_opaque = notify_opaque; in xilinx_axidma_data_stream_can_push()
429 struct Stream *s = &ds->dma->streams[1]; in xilinx_axidma_data_stream_push()
545 (Object **)&ds->dma, in xilinx_axidma_realize()
549 (Object **)&cs->dma, in xilinx_axidma_realize()
[all …]
/qemu/hw/display/
H A Domap_lcdc.c220 omap_lcd->dma->phys_framebuffer[omap_lcd->dma->current_frame], in omap_update_display()
272 size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top; in omap_update_display()
274 size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top; in omap_update_display()
286 omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame; in omap_update_display()
348 if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu, in omap_lcd_update()
351 s->dma->src].addr_valid(s->dma->mpu, in omap_lcd_update()
355 s->dma->src].addr_valid(s->dma->mpu, in omap_lcd_update()
358 s->dma->src].addr_valid(s->dma->mpu, in omap_lcd_update()
367 s->dma->phys_framebuffer[0] = s->dma->src_f1_top; in omap_lcd_update()
368 s->dma->phys_framebuffer[1] = s->dma->src_f2_top; in omap_lcd_update()
[all …]
/qemu/hw/misc/
H A Dedu.c75 } dma; member
146 if (!(edu->dma.cmd & EDU_DMA_RUN)) { in edu_dma_timer()
151 uint64_t dst = edu->dma.dst; in edu_dma_timer()
155 edu->dma_buf + dst, edu->dma.cnt); in edu_dma_timer()
157 uint64_t src = edu->dma.src; in edu_dma_timer()
161 edu->dma_buf + src, edu->dma.cnt); in edu_dma_timer()
164 edu->dma.cmd &= ~EDU_DMA_RUN; in edu_dma_timer()
165 if (edu->dma.cmd & EDU_DMA_IRQ) { in edu_dma_timer()
177 if (write && (edu->dma.cmd & EDU_DMA_RUN)) { in dma_rw()
182 *dma = *val; in dma_rw()
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/qemu/hw/ppc/
H A Dppc440_uc.c539 PPC4xxDmaState *dma = opaque; in dcr_read_dma() local
541 int addr = dcrn - dma->base; in dcr_read_dma()
574 val = dma->sr; in dcr_read_dma()
587 int addr = dcrn - dma->base; in dcr_write_dma()
671 dma->sr &= ~val; in dcr_write_dma()
682 int dma_base = dma->base; in ppc4xx_dma_reset()
684 memset(dma, 0, sizeof(*dma)); in ppc4xx_dma_reset()
685 dma->base = dma_base; in ppc4xx_dma_reset()
690 PPC4xxDmaState *dma; in ppc4xx_dma_init() local
693 dma = g_malloc0(sizeof(*dma)); in ppc4xx_dma_init()
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H A Dppc405_uc.c252 dma->cr[i] = 0x00000000; in ppc405_dma_reset()
253 dma->ct[i] = 0x00000000; in ppc405_dma_reset()
254 dma->da[i] = 0x00000000; in ppc405_dma_reset()
255 dma->sa[i] = 0x00000000; in ppc405_dma_reset()
256 dma->sg[i] = 0x00000000; in ppc405_dma_reset()
258 dma->sr = 0x00000000; in ppc405_dma_reset()
259 dma->sgc = 0x00000000; in ppc405_dma_reset()
260 dma->slp = 0x7C000000; in ppc405_dma_reset()
261 dma->pol = 0x00000000; in ppc405_dma_reset()
271 sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]); in ppc405_dma_realize()
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/qemu/hw/m68k/
H A Dnext-cube.c83 next_dma dma[10]; member
537 next_state->dma[NEXTDMA_ENRX].next = val; in next_dma_write()
568 next_state->dma[NEXTDMA_SCSI].next = val; in next_dma_write()
600 val = next_state->dma[NEXTDMA_SCSI].csr; in next_dma_read()
604 val = next_state->dma[NEXTDMA_ENRX].csr; in next_dma_read()
782 base_addr = next_state->dma[type].next; in nextdma_write()
789 next_state->dma[type].next_initbuf = 0; in nextdma_write()
792 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); in nextdma_write()
793 next_state->dma[type].saved_next = (next_state->dma[type].next); in nextdma_write()
802 next_state->dma[type].next = next_state->dma[type].start; in nextdma_write()
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/qemu/hw/microblaze/
H A Dpetalogix_ml605_mmu.c74 DeviceState *dev, *dma, *eth0; in petalogix_ml605_init() local
137 dma = qdev_new("xlnx.axi-dma"); in petalogix_ml605_init()
143 ds = object_property_get_link(OBJECT(dma), in petalogix_ml605_init()
145 cs = object_property_get_link(OBJECT(dma), in petalogix_ml605_init()
162 qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000); in petalogix_ml605_init()
163 object_property_set_link(OBJECT(dma), "axistream-connected", ds, in petalogix_ml605_init()
165 object_property_set_link(OBJECT(dma), "axistream-control-connected", cs, in petalogix_ml605_init()
167 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); in petalogix_ml605_init()
168 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR); in petalogix_ml605_init()
169 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]); in petalogix_ml605_init()
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/qemu/hw/ide/
H A Dpci.c201 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_start_dma()
223 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_prepare_buf()
278 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_rw_buf()
327 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_set_inactive()
339 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_restart_dma()
348 bmdma_set_inactive(&bm->dma, false); in bmdma_cancel()
352 static void bmdma_reset(const IDEDMA *dma) in bmdma_reset() argument
354 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_reset()
605 if (bus->dma == &bm->dma) { in bmdma_init()
609 bm->dma.ops = &bmdma_ops; in bmdma_init()
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H A Dmacio.c117 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1, in pmac_ide_atapi_transfer_cb()
185 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1, in pmac_ide_transfer_cb()
189 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1, in pmac_ide_transfer_cb()
193 s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk), &s->sg, in pmac_ide_transfer_cb()
256 if (s->bus->dma->aiocb) { in pmac_ide_flush()
381 static int ide_nop_int(const IDEDMA *dma, bool is_write) in ide_nop_int() argument
386 static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l) in ide_nop_int32() argument
391 static void ide_dbdma_start(const IDEDMA *dma, IDEState *s, in ide_dbdma_start() argument
394 MACIOIDEState *m = container_of(dma, MACIOIDEState, dma); in ide_dbdma_start()
426 s->dma.ops = &dbdma_ops; in macio_ide_realizefn()
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H A Dcore.c581 s->bus->dma->ops->pio_transfer(s->bus->dma); in ide_transfer_start_norecurse()
596 s->bus->dma->ops->cmd_done(s->bus->dma); in ide_cmd_done()
755 if (s->bus->dma->aiocb) { in ide_cancel_dma_sync()
833 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes); in dma_buf_commit()
844 s->bus->dma->ops->set_inactive(s->bus->dma, more); in ide_set_inactive()
932 prep_size = s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size); in ide_dma_cb()
1015 s->bus->dma->ops->start_dma(s->bus->dma, s, cb); in ide_start_dma()
2544 if (bus->dma->aiocb) { in ide_bus_reset()
2558 bus->dma->ops->reset(bus->dma); in ide_bus_reset()
2717 s->bus->dma->ops->restart_dma(s->bus->dma); in ide_restart_dma()
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H A Dahci.c1405 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); in ahci_pio_transfer()
1433 if (ahci_dma_prepare_buf(dma, size)) { in ahci_pio_transfer()
1467 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); in ahci_start_dma()
1482 static void ahci_restart(const IDEDMA *dma) in ahci_restart() argument
1484 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); in ahci_restart()
1501 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); in ahci_dma_prepare_buf()
1522 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); in ahci_commit_buf()
1530 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); in ahci_dma_rw_buf()
1566 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); in ahci_cmd_done()
1636 ad->port.dma = &ad->dma; in ahci_realize()
[all …]
/qemu/include/hw/arm/
H A Dsoc_dma.h45 struct soc_dma_s *dma; member
97 void soc_dma_port_add_fifo(struct soc_dma_s *dma, hwaddr virt_base,
99 void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
102 static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma, in soc_dma_port_add_fifo_in() argument
105 return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0); in soc_dma_port_add_fifo_in()
108 static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma, in soc_dma_port_add_fifo_out() argument
111 return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1); in soc_dma_port_add_fifo_out()
/qemu/hw/nvram/
H A Dfw_cfg.c338 FWCfgDmaAccess dma; in fw_cfg_dma_transfer() local
349 &dma, sizeof(dma), MEMTXATTRS_UNSPECIFIED)) { in fw_cfg_dma_transfer()
355 dma.address = be64_to_cpu(dma.address); in fw_cfg_dma_transfer()
356 dma.length = be32_to_cpu(dma.length); in fw_cfg_dma_transfer()
357 dma.control = be32_to_cpu(dma.control); in fw_cfg_dma_transfer()
377 dma.length = 0; in fw_cfg_dma_transfer()
380 dma.control = 0; in fw_cfg_dma_transfer()
382 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) { in fw_cfg_dma_transfer()
385 len = dma.length; in fw_cfg_dma_transfer()
431 dma.address += len; in fw_cfg_dma_transfer()
[all …]
/qemu/hw/block/
H A Dfdc-isa.c62 uint32_t dma; member
101 fdctrl->dma_chann = isa->dma; in isabus_fdc_realize()
104 fdctrl->dma = isa_bus_get_dma(bus, isa->dma); in isabus_fdc_realize()
105 if (!fdctrl->dma) { in isabus_fdc_realize()
109 k = ISADMA_GET_CLASS(fdctrl->dma); in isabus_fdc_realize()
110 k->register_channel(fdctrl->dma, fdctrl->dma_chann, in isabus_fdc_realize()
254 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, isa->dma)); in build_fdc_aml()
287 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
/qemu/hw/arm/
H A Dbcm2838_peripherals.c117 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n, in bcm2838_peripherals_realize()
130 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 7, in bcm2838_peripherals_realize()
132 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 8, in bcm2838_peripherals_realize()
147 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 9, in bcm2838_peripherals_realize()
149 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 10, in bcm2838_peripherals_realize()
159 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n, in bcm2838_peripherals_realize()
170 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 15, in bcm2838_peripherals_realize()
/qemu/hw/sd/
H A Domap_mmc.c30 qemu_irq *dma; member
86 qemu_irq_raise(host->dma[1]); in omap_mmc_fifolevel_update()
91 qemu_irq_lower(host->dma[1]); in omap_mmc_fifolevel_update()
97 qemu_irq_raise(host->dma[0]); in omap_mmc_fifolevel_update()
101 qemu_irq_lower(host->dma[0]); in omap_mmc_fifolevel_update()
597 qemu_irq irq, qemu_irq dma[], omap_clk clk) in omap_mmc_init() argument
602 s->dma = dma; in omap_mmc_init()
622 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], in omap2_mmc_init() argument
628 s->dma = dma; in omap2_mmc_init()
/qemu/hw/audio/
H A Dsb16.c61 uint32_t dma; member
180 int dma = s->use_hdma ? s->hdma : s->dma; in control() local
188 k->hold_DREQ(isa_dma, dma); in control()
192 k->release_DREQ(isa_dma, dma); in control()
1130 int dma, hdma; in mixer_write_datab() local
1132 dma = ctz32 (val & 0xf); in mixer_write_datab()
1134 if (dma != s->dma || hdma != s->hdma) { in mixer_write_datab()
1136 " %d(%d), 16bit %d(%d) (val=%#x)\n", dma, s->dma, in mixer_write_datab()
1140 s->dma = dma; in mixer_write_datab()
1410 s->isa_dma = isa_bus_get_dma(bus, s->dma); in sb16_realizefn()
[all …]
H A Dcs4231a.c78 uint32_t dma; member
341 k->hold_DREQ(s->isa_dma, s->dma); in cs_reset_voices()
349 k->release_DREQ(s->isa_dma, s->dma); in cs_reset_voices()
358 k->release_DREQ(s->isa_dma, s->dma); in cs_reset_voices()
467 k->release_DREQ(s->isa_dma, s->dma); in cs_write()
616 k->release_DREQ(s->isa_dma, s->dma); in cs4231a_pre_load()
675 s->isa_dma = isa_bus_get_dma(bus, s->dma); in cs4231a_realizefn()
687 k->register_channel(s->isa_dma, s->dma, cs_dma_read, s); in cs4231a_realizefn()
696 DEFINE_PROP_UINT32 ("dma", CSState, dma, 3),
/qemu/hw/isa/
H A Disa-bus.c110 assert(!bus->dma[0] && !bus->dma[1]); in isa_bus_dma()
111 bus->dma[0] = dma8; in isa_bus_dma()
112 bus->dma[1] = dma16; in isa_bus_dma()
118 return bus->dma[nchan > 3 ? 1 : 0]; in isa_bus_get_dma()
/qemu/include/hw/mips/
H A Dmips.h17 void rc4030_dma_read(void *dma, uint8_t *buf, int len);
18 void rc4030_dma_write(void *dma, uint8_t *buf, int len);
/qemu/tests/qemu-iotests/
H A D172.out14 dma = 2 (0x2)
43 dma = 2 (0x2)
82 dma = 2 (0x2)
139 dma = 2 (0x2)
197 dma = 2 (0x2)
240 dma = 2 (0x2)
279 dma = 2 (0x2)
336 dma = 2 (0x2)
397 dma = 2 (0x2)
436 dma = 2 (0x2)
[all …]
/qemu/hw/i2c/
H A Domap_i2c.c45 uint16_t dma; member
64 if ((s->dma >> 15) & 1) /* RDMA_EN */ in omap_i2c_interrupts_update()
66 if ((s->dma >> 7) & 1) /* XDMA_EN */ in omap_i2c_interrupts_update()
144 s->dma = 0; in omap_i2c_reset()
192 return s->dma; in omap_i2c_read()
292 s->dma = value & 0x8080; in omap_i2c_write()
/qemu/include/sysemu/
H A Dxen-mapcache.h22 uint8_t lock, bool dma,
41 bool dma, in xen_map_cache() argument

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