/qemu/linux-user/xtensa/ |
H A D | cpu_loop.c | 29 env->pc = env->sregs[EPC1]; in xtensa_rfw() 46 put_user_ual(env->regs[0], env->regs[5] - 16); in xtensa_overflow4() 47 put_user_ual(env->regs[1], env->regs[5] - 12); in xtensa_overflow4() 48 put_user_ual(env->regs[2], env->regs[5] - 8); in xtensa_overflow4() 49 put_user_ual(env->regs[3], env->regs[5] - 4); in xtensa_overflow4() 55 get_user_ual(env->regs[0], env->regs[5] - 16); in xtensa_underflow4() 56 get_user_ual(env->regs[1], env->regs[5] - 12); in xtensa_underflow4() 57 get_user_ual(env->regs[2], env->regs[5] - 8); in xtensa_underflow4() 58 get_user_ual(env->regs[3], env->regs[5] - 4); in xtensa_underflow4() 64 put_user_ual(env->regs[0], env->regs[9] - 16); in xtensa_overflow8() [all …]
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/qemu/target/sparc/ |
H A D | win_helper.c | 42 if (env->cwp == env->nwindows - 1) { in cpu_set_cwp() 43 memcpy32(env->regbase, env->regbase + env->nwindows * 16); in cpu_set_cwp() 49 memcpy32(env->regbase + env->nwindows * 16, env->regbase); in cpu_set_cwp() 144 cwp = cpu_cwp_inc(env, env->cwp + 1) ; in helper_rett() 149 env->psrs = env->psrps; in helper_rett() 158 cwp = cpu_cwp_dec(env, env->cwp - 1); in helper_save() 169 cwp = cpu_cwp_inc(env, env->cwp + 1); in helper_restore() 200 cwp = cpu_cwp_dec(env, env->cwp - 1); in helper_save() 361 dst = get_gl_gregset(env, env->gl); in cpu_gl_switch_gregs() 444 env->hpstate = env->htstate[env->tl]; in helper_done() [all …]
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H A D | int64_helper.c | 178 if (env->tl >= env->maxtl) { in sparc_cpu_do_interrupt() 184 if (env->tl < env->maxtl - 1) { in sparc_cpu_do_interrupt() 188 if (env->tl < env->maxtl) { in sparc_cpu_do_interrupt() 200 env->htstate[env->tl] = env->hpstate; in sparc_cpu_do_interrupt() 209 cpu_gl_switch_gregs(env, env->gl + 1); in sparc_cpu_do_interrupt() 241 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); in sparc_cpu_do_interrupt() 243 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); in sparc_cpu_do_interrupt() 245 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); in sparc_cpu_do_interrupt() 251 env->pc = env->tbr & ~0x7fffULL; in sparc_cpu_do_interrupt() 254 env->npc = env->pc + 4; in sparc_cpu_do_interrupt() [all …]
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/qemu/target/i386/ |
H A D | helper.h | 5 DEF_HELPER_1(read_eflags, tl, env) 6 DEF_HELPER_2(divb_AL, void, env, tl) 27 DEF_HELPER_1(aaa, void, env) 28 DEF_HELPER_1(aas, void, env) 29 DEF_HELPER_1(daa, void, env) 30 DEF_HELPER_1(das, void, env) 32 DEF_HELPER_2(lsl, tl, env, tl) 33 DEF_HELPER_2(lar, tl, env, tl) 45 DEF_HELPER_1(clts, void, env) 63 DEF_HELPER_1(rsm, void, env) [all …]
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H A D | machine.c | 222 CPUX86State *env = &cpu->env; in cpu_pre_save() local 317 CPUX86State *env = &cpu->env; in cpu_post_load() local 439 CPUX86State *env = &cpu->env; in exception_info_needed() local 531 CPUX86State *env = &cpu->env; in fpop_ip_dp_needed() local 533 return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0; in fpop_ip_dp_needed() 552 CPUX86State *env = &cpu->env; in tsc_adjust_needed() local 571 CPUX86State *env = &cpu->env; in msr_smi_count_needed() local 590 CPUX86State *env = &cpu->env; in tscdeadline_needed() local 609 CPUX86State *env = &cpu->env; in misc_enable_needed() local 617 CPUX86State *env = &cpu->env; in feature_control_needed() local [all …]
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/qemu/target/i386/tcg/sysemu/ |
H A D | svm_helper.c | 102 if ((env->efer & MSR_EFER_LME) && (env->cr[0] & CR0_PG_MASK) in is_efer_invalid_state() 107 if ((env->efer & MSR_EFER_LME) && (env->cr[0] & CR0_PG_MASK) in is_efer_invalid_state() 112 if ((env->efer & MSR_EFER_LME) && (env->cr[0] & CR0_PG_MASK) in is_efer_invalid_state() 238 env->intercept_cr_read = x86_lduw_phys(cs, env->vm_vmcb + in helper_vmrun() 244 env->intercept_dr_read = x86_lduw_phys(cs, env->vm_vmcb + in helper_vmrun() 297 env->tsc_offset = x86_ldq_phys(cs, env->vm_vmcb + in helper_vmrun() 428 env->exception_next_eip = env->eip; in helper_vmrun() 447 env->exception_next_eip = env->eip; in helper_vmrun() 511 svm_canonicalization(env, &env->kernelgsbase); in helper_vmload() 860 env->regs[R_ESP] = x86_ldq_phys(cs, env->vm_hsave + in do_vmexit() [all …]
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H A D | misc_helper.c | 197 cpu_load_efer(env, (env->efer & ~update_mask) | in helper_wrmsr() 248 env->mtrr_var[((uint32_t)env->regs[R_ECX] - in helper_wrmsr() 259 env->mtrr_var[((uint32_t)env->regs[R_ECX] - in helper_wrmsr() 263 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_wrmsr() 268 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_wrmsr() 279 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_wrmsr() 413 val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - in helper_rdmsr() 424 val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - in helper_rdmsr() 432 val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_rdmsr() 443 val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_rdmsr() [all …]
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/qemu/target/rx/ |
H A D | op_helper.c | 40 env->isp = env->regs[0]; in _set_psw() 41 env->regs[0] = env->usp; in _set_psw() 43 env->usp = env->regs[0]; in _set_psw() 44 env->regs[0] = env->isp; in _set_psw() 83 env->fpsw = FIELD_DP32(env->fpsw, FPSW, CAUSE, 0); in update_fpsw() 161 env->psw_s = env->psw_o = 0; in FLOATOP() 241 cpu_stfn[sz](env, env->regs[1], env->regs[2], GETPC()); in helper_sstr() 300 env->psw_z = tmp - env->regs[2]; in helper_suntil() 301 env->psw_c = (tmp <= env->regs[2]); in helper_suntil() 319 env->psw_z = env->regs[3]; in helper_swhile() [all …]
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/qemu/target/ppc/ |
H A D | excp_helper.c | 294 CPUPPCState *env = &cpu->env; in ppc_excp_apply_ail() local 391 CPUPPCState *env = &cpu->env; in powerpc_reset_excp_state() local 401 CPUPPCState *env = &cpu->env; in powerpc_set_excp_state() local 484 CPUPPCState *env = &cpu->env; in powerpc_excp_40x() local 585 env->spr[srr0] = env->nip; in powerpc_excp_40x() 1208 env->spr[srr0] = env->nip; in powerpc_excp_booke() 1318 return is_prefix_insn(env, ppc_ldl_code(env, env->nip)); in is_prefix_insn_excp() 1494 env->lr = env->nip; in powerpc_excp_books() 2668 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); in helper_rfid() 2673 do_rfi(env, env->lr, env->ctr); in helper_rfscv() [all …]
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/qemu/target/mips/tcg/sysemu/ |
H A D | cp0_helper.c | 38 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi() local 50 CPUMIPSState *env = &c->env; in mips_vp_is_wfi() local 410 return env->CP0_MAAR[env->CP0_MAARI] >> 32; in helper_mfhc0_maar() 488 return env->CP0_MAAR[env->CP0_MAARI]; in helper_dmfc0_maar() 1272 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) | in helper_mtc0_config4() 1278 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | in helper_mtc0_config5() 1297 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env); in helper_mtc0_maar() 1302 env->CP0_MAAR[env->CP0_MAARI] = in helper_mthc0_maar() 1580 if (&other_cpu->env != env) { in helper_dvpe() 1596 if (&other_cpu->env != env in helper_evpe() [all …]
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H A D | tlb_helper.c | 275 env->tlb->helper_tlbwi(env); in helper_tlbwi() 280 env->tlb->helper_tlbwr(env); in helper_tlbwr() 285 env->tlb->helper_tlbp(env); in helper_tlbp() 290 env->tlb->helper_tlbr(env); in helper_tlbr() 295 env->tlb->helper_tlbinv(env); in helper_tlbinv() 300 env->tlb->helper_tlbinvf(env); in helper_tlbinvf() 562 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | in raise_mmu_exception() 566 env->CP0_EntryHi &= env->SEGMask; in raise_mmu_exception() 1020 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC); in set_badinstr_registers() 1031 CPUMIPSState *env = &cpu->env; in mips_cpu_do_interrupt() local [all …]
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/qemu/target/riscv/ |
H A D | fpu_helper.c | 222 return nanbox_s(env, float32_add(frs1, frs2, &env->fp_status)); in helper_fadd_s() 229 return nanbox_s(env, float32_sub(frs1, frs2, &env->fp_status)); in helper_fsub_s() 236 return nanbox_s(env, float32_mul(frs1, frs2, &env->fp_status)); in helper_fmul_s() 243 return nanbox_s(env, float32_div(frs1, frs2, &env->fp_status)); in helper_fdiv_s() 250 return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmin_s() 267 return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmax_s() 283 return nanbox_s(env, float32_sqrt(frs1, &env->fp_status)); in helper_fsqrt_s() 357 return nanbox_s(env, int64_to_float32(rs1, &env->fp_status)); in helper_fcvt_s_l() 583 return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmin_h() 600 return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmax_h() [all …]
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H A D | op_helper.c | 140 if ((env->priv < PRV_M) && !get_field(env->menvcfg, envbits)) { in check_zicbo_envcfg() 145 (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) || in check_zicbo_envcfg() 146 ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) { in check_zicbo_envcfg() 150 if ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)) { in check_zicbo_envcfg() 278 if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { in helper_sret() 282 if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) { in helper_sret() 297 if (riscv_has_ext(env, RVH) && !env->virt_enabled) { in helper_sret() 385 if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) && in helper_wrs_nto() 399 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)))) { in helper_tlb_flush() 424 (env->priv == PRV_S && !env->virt_enabled)) { in helper_hyp_tlb_flush() [all …]
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/qemu/target/arm/tcg/ |
H A D | m_helper.c | 217 CPUARMState *env = &cpu->env; in v7m_stack_write() local 305 CPUARMState *env = &cpu->env; in v7m_stack_read() local 660 CPUARMState *env = &cpu->env; in arm_v7m_load_vector() local 764 CPUARMState *env = &cpu->env; in v7m_push_callee_stack() local 841 CPUARMState *env = &cpu->env; in v7m_exception_taken() local 1185 CPUARMState *env = &cpu->env; in v7m_push_stack() local 1359 CPUARMState *env = &cpu->env; in do_v7m_exception_exit() local 1917 CPUARMState *env = &cpu->env; in do_v7m_function_return() local 1994 CPUARMState *env = &cpu->env; in v7m_read_half_insn() local 2042 CPUARMState *env = &cpu->env; in v7m_read_sg_stack_word() local [all …]
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H A D | helper-mve.h | 19 DEF_HELPER_FLAGS_3(mve_vldrb, TCG_CALL_NO_WG, void, env, ptr, i32) 20 DEF_HELPER_FLAGS_3(mve_vldrh, TCG_CALL_NO_WG, void, env, ptr, i32) 21 DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32) 22 DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32) 23 DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32) 24 DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32) 26 DEF_HELPER_FLAGS_3(mve_vldrb_sh, TCG_CALL_NO_WG, void, env, ptr, i32) 32 DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32) 33 DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32) 217 DEF_HELPER_FLAGS_1(mve_vpnot, TCG_CALL_NO_WG, void, env) [all …]
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/qemu/linux-user/sparc/ |
H A D | cpu_loop.c | 68 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & in save_window() 70 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); in save_window() 77 save_window_offset(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); in save_window() 92 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & in restore_window() 97 cwp1 = cpu_cwp_inc(env, env->cwp + 1); in restore_window() 114 if (env->cleanwin < env->nwindows - 1) in restore_window() 142 cwp1 = cpu_cwp_inc(env, env->cwp + 1); in flush_windows() 154 env->pc = env->npc; in next_instruction() 155 env->npc = env->npc + 4; in next_instruction() 243 env->pc = env->npc; in cpu_loop() [all …]
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/qemu/target/mips/ |
H A D | cpu.c | 90 env->hflags, env->btarget, env->bcond); in mips_cpu_dump_state() 104 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); in mips_cpu_dump_state() 107 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); in mips_cpu_dump_state() 193 CPUMIPSState *env = &cpu->env; in mips_cpu_reset_hold() local 222 env->CCRes = env->cpu_model->CCRes; in mips_cpu_reset_hold() 253 env->msair = env->cpu_model->MSAIR; in mips_cpu_reset_hold() 450 CPUMIPSState *env = &cpu->env; in mips_cp0_period_set() local 461 CPUMIPSState *env = &cpu->env; in mips_cpu_realizefn() local 488 mmu_init(env, env->cpu_model); in mips_cpu_realizefn() 490 fpu_init(env, env->cpu_model); in mips_cpu_realizefn() [all …]
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/qemu/target/mips/tcg/ |
H A D | sysemu_helper.h.inc | 18 DEF_HELPER_1(mfc0_random, tl, env) 21 DEF_HELPER_1(mfc0_tcbind, tl, env) 37 DEF_HELPER_1(mftc0_epc, tl, env) 41 DEF_HELPER_1(mfc0_maar, tl, env) 147 DEF_HELPER_1(mftdsp, tl, env) 155 DEF_HELPER_1(dvpe, tl, env) 156 DEF_HELPER_1(evpe, tl, env) 159 DEF_HELPER_1(dvp, tl, env) 160 DEF_HELPER_1(evp, tl, env) 172 DEF_HELPER_1(di, tl, env) [all …]
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H A D | fpu_helper.c | 98 compute_hflags(env); in helper_ctc1() 110 compute_hflags(env); in helper_ctc1() 122 compute_hflags(env); in helper_ctc1() 134 compute_hflags(env); in helper_ctc1() 143 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | in helper_ctc1() 151 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | in helper_ctc1() 158 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | in helper_ctc1() 163 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) | in helper_ctc1() 164 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask)); in helper_ctc1() 172 restore_fp_status(env); in helper_ctc1() [all …]
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/qemu/target/xtensa/ |
H A D | exc_helper.c | 81 HELPER(debug_exception)(env, env->pc, cause); in debug_exception_env() 92 env->sregs[EPS2 + level - 2] = env->sregs[PS]; in HELPER() 105 env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | in HELPER() 176 env->sregs[EPC1 + level - 1] = env->pc; in handle_interrupt() 180 env->pc = relocated_vector(env, in handle_interrupt() 190 env->sregs[DEPC] = env->pc; in handle_interrupt() 192 env->sregs[EPC1] = env->pc; in handle_interrupt() 196 env->sregs[EPC1] = env->pc; in handle_interrupt() 218 env->pc, env->regs[0], env->sregs[PS], in xtensa_cpu_do_interrupt() 238 env->pc, env->regs[0], env->sregs[PS], in xtensa_cpu_do_interrupt() [all …]
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H A D | win_helper.c | 40 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys() 44 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys() 46 memcpy(env->regs + window + n1, env->phys_regs, in copy_window_from_phys() 56 memcpy(env->phys_regs + phys, env->regs + window, in copy_phys_from_window() 60 memcpy(env->phys_regs + phys, env->regs + window, in copy_phys_from_window() 62 memcpy(env->phys_regs, env->regs + window + n1, in copy_phys_from_window() 110 env->sregs[WINDOW_START] |= windowstart_bit(env->windowbase_next, env); in HELPER() 123 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | in HELPER() 125 env->sregs[EPC1] = env->pc = pc; in HELPER() 173 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | in HELPER() [all …]
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/qemu/target/sh4/ |
H A D | op_helper.c | 54 cpu_load_tlb(env); in helper_ldtlb() 62 CPUState *cs = env_cpu(env); in raise_exception() 93 env->in_sleep = 1; in helper_sleep() 99 env->tra = tra << 2; in helper_trapa() 134 env->movcal_backup_tail = &(env->movcal_backup); in helper_discard_movcal_backup() 166 int64_t mac = env->mac; in helper_macl() 177 env->mac = res; in helper_macl() 196 env->mach = 1; in helper_macw() 198 env->macl = res; in helper_macw() 201 env->mac += mul; in helper_macw() [all …]
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/qemu/target/hppa/ |
H A D | gdbstub.c | 40 val = env->gr[n]; in hppa_cpu_gdb_read_register() 46 val = env->iaoq_f; in hppa_cpu_gdb_read_register() 52 val = env->iaoq_b; in hppa_cpu_gdb_read_register() 115 val = env->cr[24]; in hppa_cpu_gdb_read_register() 118 val = env->cr[25]; in hppa_cpu_gdb_read_register() 121 val = env->cr[26]; in hppa_cpu_gdb_read_register() 124 val = env->cr[27]; in hppa_cpu_gdb_read_register() 127 val = env->cr[28]; in hppa_cpu_gdb_read_register() 160 env->gr[n] = val; in hppa_cpu_gdb_write_register() 163 env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31); in hppa_cpu_gdb_write_register() [all …]
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/qemu/target/m68k/ |
H A D | op_helper.c | 206 do_m68k_semihosting(env, env->dregs[0]); in cf_interrupt_all() 213 sr = env->sr | cpu_m68k_get_ccr(env); in cf_interrupt_all() 218 vector, env->pc, env->aregs[7], sr); in cf_interrupt_all() 227 env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT); in cf_interrupt_all() 242 env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0); in cf_interrupt_all() 293 sr = env->sr | cpu_m68k_get_ccr(env); in m68k_interrupt_all() 298 vector, env->pc, env->aregs[7], sr); in m68k_interrupt_all() 379 env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc); in m68k_interrupt_all() 395 do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); in m68k_interrupt_all() 420 env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0); in m68k_interrupt_all() [all …]
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/qemu/target/i386/tcg/ |
H A D | seg_helper.c | 371 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX], retaddr); in switch_tss_ra() 372 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX], retaddr); in switch_tss_ra() 373 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX], retaddr); in switch_tss_ra() 840 env->tr.base, env->tr.limit); in get_rsp_from_tss() 1007 env->eip = env->regs[R_ECX]; in helper_sysret() 1030 env->eip = (uint32_t)env->regs[R_ECX]; in helper_sysret() 1086 CPUX86State *env = &cpu->env; in do_interrupt_all() local 2183 env->regs[R_ESP] = env->sysenter_esp; in helper_sysenter() 2184 env->eip = env->sysenter_eip; in helper_sysenter() 2222 env->regs[R_ESP] = env->regs[R_ECX]; in helper_sysexit() [all …]
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