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Searched refs:fcsr0 (Results 1 – 10 of 10) sorted by relevance

/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_fmov.c.inc97 tcg_gen_st32_i64(Rj, tcg_env, offsetof(CPULoongArchState, fcsr0));
99 TCGv_i32 fcsr0 = tcg_temp_new_i32();
102 tcg_gen_ld_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0));
105 tcg_gen_andi_i32(fcsr0, fcsr0, ~mask);
106 tcg_gen_or_i32(fcsr0, fcsr0, temp);
107 tcg_gen_st_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0));
130 tcg_gen_ld32u_i64(dest, tcg_env, offsetof(CPULoongArchState, fcsr0));
/qemu/linux-user/loongarch64/
H A Dcpu_loop.c55 if (GET_FP_CAUSE(env->fcsr0) & FP_INVALID) { in cpu_loop()
57 } else if (GET_FP_CAUSE(env->fcsr0) & FP_DIV0) { in cpu_loop()
59 } else if (GET_FP_CAUSE(env->fcsr0) & FP_OVERFLOW) { in cpu_loop()
61 } else if (GET_FP_CAUSE(env->fcsr0) & FP_UNDERFLOW) { in cpu_loop()
63 } else if (GET_FP_CAUSE(env->fcsr0) & FP_INEXACT) { in cpu_loop()
H A Dsignal.c185 __put_user(env->fcsr0, &lasx_ctx->fcsr); in setup_sigframe()
200 __put_user(env->fcsr0, &lsx_ctx->fcsr); in setup_sigframe()
214 __put_user(env->fcsr0, &fpu_ctx->fcsr); in setup_sigframe()
302 __get_user(env->fcsr0, &lasx_ctx->fcsr); in restore_sigframe()
314 __get_user(env->fcsr0, &lsx_ctx->fcsr); in restore_sigframe()
325 __get_user(env->fcsr0, &fpu_ctx->fcsr); in restore_sigframe()
/qemu/target/loongarch/
H A Dgdbstub.c95 return gdb_get_reg32(mem_buf, env->fcsr0); in loongarch_gdb_get_fpu()
113 env->fcsr0 = ldl_p(mem_buf); in loongarch_gdb_set_fpu()
H A Dmachine.c42 VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
H A Dcpu.c511 env->fcsr0 = 0x0; in loongarch_cpu_reset_hold()
687 qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0); in loongarch_cpu_dump_state()
H A Dcpu.h290 uint32_t fcsr0; member
/qemu/target/loongarch/tcg/
H A Dfpu_helper.c31 set_float_rounding_mode(ieee_rm[(env->fcsr0 >> FCSR0_RM) & 0x3], in restore_fp_status()
66 SET_FP_CAUSE(env->fcsr0, flags); in update_fcsr0_mask()
70 SET_FP_CAUSE(env->fcsr0, flags); in update_fcsr0_mask()
73 if (GET_FP_ENABLES(env->fcsr0) & flags) { in update_fcsr0_mask()
76 UPDATE_FP_FLAGS(env->fcsr0, flags); in update_fcsr0_mask()
877 set_float_rounding_mode(ieee_rm[(env->fcsr0 >> FCSR0_RM) & 0x3], in helper_set_rounding_mode()
H A Dvec_helper.c2385 UPDATE_FP_CAUSE(env->fcsr0, flags); in vec_update_fcsr0_mask()
2388 if (GET_FP_ENABLES(env->fcsr0) & flags) { in vec_update_fcsr0_mask()
2391 UPDATE_FP_FLAGS(env->fcsr0, flags); in vec_update_fcsr0_mask()
2402 SET_FP_CAUSE(env->fcsr0, 0); in vec_clear_cause()
/qemu/target/loongarch/kvm/
H A Dkvm.c436 env->fcsr0 = fpu.fcsr; in kvm_loongarch_get_regs_fp()
457 fpu.fcsr = env->fcsr0; in kvm_loongarch_put_regs_fp()