1 /*
2 * ARM VFP floating-point operations
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "internals.h"
24 #include "cpu-features.h"
25 #ifdef CONFIG_TCG
26 #include "qemu/log.h"
27 #include "fpu/softfloat.h"
28 #endif
29
30 /* VFP support. We follow the convention used for VFP instructions:
31 Single precision routines have a "s" suffix, double precision a
32 "d" suffix. */
33
34 #ifdef CONFIG_TCG
35
36 /* Convert host exception flags to vfp form. */
vfp_exceptbits_from_host(int host_bits)37 static inline int vfp_exceptbits_from_host(int host_bits)
38 {
39 int target_bits = 0;
40
41 if (host_bits & float_flag_invalid) {
42 target_bits |= 1;
43 }
44 if (host_bits & float_flag_divbyzero) {
45 target_bits |= 2;
46 }
47 if (host_bits & float_flag_overflow) {
48 target_bits |= 4;
49 }
50 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
51 target_bits |= 8;
52 }
53 if (host_bits & float_flag_inexact) {
54 target_bits |= 0x10;
55 }
56 if (host_bits & float_flag_input_denormal) {
57 target_bits |= 0x80;
58 }
59 return target_bits;
60 }
61
62 /* Convert vfp exception flags to target form. */
vfp_exceptbits_to_host(int target_bits)63 static inline int vfp_exceptbits_to_host(int target_bits)
64 {
65 int host_bits = 0;
66
67 if (target_bits & 1) {
68 host_bits |= float_flag_invalid;
69 }
70 if (target_bits & 2) {
71 host_bits |= float_flag_divbyzero;
72 }
73 if (target_bits & 4) {
74 host_bits |= float_flag_overflow;
75 }
76 if (target_bits & 8) {
77 host_bits |= float_flag_underflow;
78 }
79 if (target_bits & 0x10) {
80 host_bits |= float_flag_inexact;
81 }
82 if (target_bits & 0x80) {
83 host_bits |= float_flag_input_denormal;
84 }
85 return host_bits;
86 }
87
vfp_get_fpscr_from_host(CPUARMState * env)88 static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
89 {
90 uint32_t i;
91
92 i = get_float_exception_flags(&env->vfp.fp_status);
93 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
94 /* FZ16 does not generate an input denormal exception. */
95 i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
96 & ~float_flag_input_denormal);
97 i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
98 & ~float_flag_input_denormal);
99 return vfp_exceptbits_from_host(i);
100 }
101
vfp_set_fpscr_to_host(CPUARMState * env,uint32_t val)102 static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
103 {
104 int i;
105 uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
106
107 changed ^= val;
108 if (changed & (3 << 22)) {
109 i = (val >> 22) & 3;
110 switch (i) {
111 case FPROUNDING_TIEEVEN:
112 i = float_round_nearest_even;
113 break;
114 case FPROUNDING_POSINF:
115 i = float_round_up;
116 break;
117 case FPROUNDING_NEGINF:
118 i = float_round_down;
119 break;
120 case FPROUNDING_ZERO:
121 i = float_round_to_zero;
122 break;
123 }
124 set_float_rounding_mode(i, &env->vfp.fp_status);
125 set_float_rounding_mode(i, &env->vfp.fp_status_f16);
126 }
127 if (changed & FPCR_FZ16) {
128 bool ftz_enabled = val & FPCR_FZ16;
129 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
130 set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
131 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
132 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
133 }
134 if (changed & FPCR_FZ) {
135 bool ftz_enabled = val & FPCR_FZ;
136 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
137 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
138 }
139 if (changed & FPCR_DN) {
140 bool dnan_enabled = val & FPCR_DN;
141 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
142 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
143 }
144
145 /*
146 * The exception flags are ORed together when we read fpscr so we
147 * only need to preserve the current state in one of our
148 * float_status values.
149 */
150 i = vfp_exceptbits_to_host(val);
151 set_float_exception_flags(i, &env->vfp.fp_status);
152 set_float_exception_flags(0, &env->vfp.fp_status_f16);
153 set_float_exception_flags(0, &env->vfp.standard_fp_status);
154 set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
155 }
156
157 #else
158
vfp_get_fpscr_from_host(CPUARMState * env)159 static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
160 {
161 return 0;
162 }
163
vfp_set_fpscr_to_host(CPUARMState * env,uint32_t val)164 static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
165 {
166 }
167
168 #endif
169
HELPER(vfp_get_fpscr)170 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
171 {
172 uint32_t i, fpscr;
173
174 fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
175 | (env->vfp.vec_len << 16)
176 | (env->vfp.vec_stride << 20);
177
178 /*
179 * M-profile LTPSIZE overlaps A-profile Stride; whichever of the
180 * two is not applicable to this CPU will always be zero.
181 */
182 fpscr |= env->v7m.ltpsize << 16;
183
184 fpscr |= vfp_get_fpscr_from_host(env);
185
186 i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
187 fpscr |= i ? FPCR_QC : 0;
188
189 return fpscr;
190 }
191
vfp_get_fpscr(CPUARMState * env)192 uint32_t vfp_get_fpscr(CPUARMState *env)
193 {
194 return HELPER(vfp_get_fpscr)(env);
195 }
196
HELPER(vfp_set_fpscr)197 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
198 {
199 ARMCPU *cpu = env_archcpu(env);
200
201 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
202 if (!cpu_isar_feature(any_fp16, cpu)) {
203 val &= ~FPCR_FZ16;
204 }
205
206 vfp_set_fpscr_to_host(env, val);
207
208 if (!arm_feature(env, ARM_FEATURE_M)) {
209 /*
210 * Short-vector length and stride; on M-profile these bits
211 * are used for different purposes.
212 * We can't make this conditional be "if MVFR0.FPShVec != 0",
213 * because in v7A no-short-vector-support cores still had to
214 * allow Stride/Len to be written with the only effect that
215 * some insns are required to UNDEF if the guest sets them.
216 */
217 env->vfp.vec_len = extract32(val, 16, 3);
218 env->vfp.vec_stride = extract32(val, 20, 2);
219 } else if (cpu_isar_feature(aa32_mve, cpu)) {
220 env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT,
221 FPCR_LTPSIZE_LENGTH);
222 }
223
224 if (arm_feature(env, ARM_FEATURE_NEON) ||
225 cpu_isar_feature(aa32_mve, cpu)) {
226 /*
227 * The bit we set within fpscr_q is arbitrary; the register as a
228 * whole being zero/non-zero is what counts.
229 * TODO: M-profile MVE also has a QC bit.
230 */
231 env->vfp.qc[0] = val & FPCR_QC;
232 env->vfp.qc[1] = 0;
233 env->vfp.qc[2] = 0;
234 env->vfp.qc[3] = 0;
235 }
236
237 /*
238 * We don't implement trapped exception handling, so the
239 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
240 *
241 * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
242 * fp_status; QC, Len and Stride are stored separately earlier.
243 * Clear out all of those and the RES0 bits: only NZCV, AHP, DN,
244 * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR].
245 */
246 env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
247 }
248
vfp_set_fpscr(CPUARMState * env,uint32_t val)249 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
250 {
251 HELPER(vfp_set_fpscr)(env, val);
252 }
253
254 #ifdef CONFIG_TCG
255
256 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
257
258 #define VFP_BINOP(name) \
259 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
260 { \
261 float_status *fpst = fpstp; \
262 return float16_ ## name(a, b, fpst); \
263 } \
264 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
265 { \
266 float_status *fpst = fpstp; \
267 return float32_ ## name(a, b, fpst); \
268 } \
269 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
270 { \
271 float_status *fpst = fpstp; \
272 return float64_ ## name(a, b, fpst); \
273 }
274 VFP_BINOP(add)
VFP_BINOP(sub)275 VFP_BINOP(sub)
276 VFP_BINOP(mul)
277 VFP_BINOP(div)
278 VFP_BINOP(min)
279 VFP_BINOP(max)
280 VFP_BINOP(minnum)
281 VFP_BINOP(maxnum)
282 #undef VFP_BINOP
283
284 dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env)
285 {
286 return float16_sqrt(a, &env->vfp.fp_status_f16);
287 }
288
VFP_HELPER(sqrt,s)289 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
290 {
291 return float32_sqrt(a, &env->vfp.fp_status);
292 }
293
VFP_HELPER(sqrt,d)294 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
295 {
296 return float64_sqrt(a, &env->vfp.fp_status);
297 }
298
softfloat_to_vfp_compare(CPUARMState * env,FloatRelation cmp)299 static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
300 {
301 uint32_t flags;
302 switch (cmp) {
303 case float_relation_equal:
304 flags = 0x6;
305 break;
306 case float_relation_less:
307 flags = 0x8;
308 break;
309 case float_relation_greater:
310 flags = 0x2;
311 break;
312 case float_relation_unordered:
313 flags = 0x3;
314 break;
315 default:
316 g_assert_not_reached();
317 }
318 env->vfp.xregs[ARM_VFP_FPSCR] =
319 deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags);
320 }
321
322 /* XXX: check quiet/signaling case */
323 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \
324 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
325 { \
326 softfloat_to_vfp_compare(env, \
327 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \
328 } \
329 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
330 { \
331 softfloat_to_vfp_compare(env, \
332 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
333 }
DO_VFP_cmp(h,float16,dh_ctype_f16,fp_status_f16)334 DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16)
335 DO_VFP_cmp(s, float32, float32, fp_status)
336 DO_VFP_cmp(d, float64, float64, fp_status)
337 #undef DO_VFP_cmp
338
339 /* Integer to float and float to integer conversions */
340
341 #define CONV_ITOF(name, ftype, fsz, sign) \
342 ftype HELPER(name)(uint32_t x, void *fpstp) \
343 { \
344 float_status *fpst = fpstp; \
345 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
346 }
347
348 #define CONV_FTOI(name, ftype, fsz, sign, round) \
349 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
350 { \
351 float_status *fpst = fpstp; \
352 if (float##fsz##_is_any_nan(x)) { \
353 float_raise(float_flag_invalid, fpst); \
354 return 0; \
355 } \
356 return float##fsz##_to_##sign##int32##round(x, fpst); \
357 }
358
359 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
360 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
361 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
362 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
363
364 FLOAT_CONVS(si, h, uint32_t, 16, )
365 FLOAT_CONVS(si, s, float32, 32, )
366 FLOAT_CONVS(si, d, float64, 64, )
367 FLOAT_CONVS(ui, h, uint32_t, 16, u)
368 FLOAT_CONVS(ui, s, float32, 32, u)
369 FLOAT_CONVS(ui, d, float64, 64, u)
370
371 #undef CONV_ITOF
372 #undef CONV_FTOI
373 #undef FLOAT_CONVS
374
375 /* floating point conversion */
376 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
377 {
378 return float32_to_float64(x, &env->vfp.fp_status);
379 }
380
VFP_HELPER(fcvts,d)381 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
382 {
383 return float64_to_float32(x, &env->vfp.fp_status);
384 }
385
HELPER(bfcvt)386 uint32_t HELPER(bfcvt)(float32 x, void *status)
387 {
388 return float32_to_bfloat16(x, status);
389 }
390
HELPER(bfcvt_pair)391 uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status)
392 {
393 bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status);
394 bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status);
395 return deposit32(lo, 16, 16, hi);
396 }
397
398 /*
399 * VFP3 fixed point conversion. The AArch32 versions of fix-to-float
400 * must always round-to-nearest; the AArch64 ones honour the FPSCR
401 * rounding mode. (For AArch32 Neon the standard-FPSCR is set to
402 * round-to-nearest so either helper will work.) AArch32 float-to-fix
403 * must round-to-zero.
404 */
405 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
406 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
407 void *fpstp) \
408 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
409
410 #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
411 ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
412 uint32_t shift, \
413 void *fpstp) \
414 { \
415 ftype ret; \
416 float_status *fpst = fpstp; \
417 FloatRoundMode oldmode = fpst->float_rounding_mode; \
418 fpst->float_rounding_mode = float_round_nearest_even; \
419 ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \
420 fpst->float_rounding_mode = oldmode; \
421 return ret; \
422 }
423
424 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
425 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
426 void *fpst) \
427 { \
428 if (unlikely(float##fsz##_is_any_nan(x))) { \
429 float_raise(float_flag_invalid, fpst); \
430 return 0; \
431 } \
432 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
433 }
434
435 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \
436 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
437 VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
438 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
439 float_round_to_zero, _round_to_zero) \
440 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
441 get_float_rounding_mode(fpst), )
442
443 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \
444 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
445 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
446 get_float_rounding_mode(fpst), )
447
448 VFP_CONV_FIX(sh, d, 64, float64, 64, int16)
449 VFP_CONV_FIX(sl, d, 64, float64, 64, int32)
450 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64)
451 VFP_CONV_FIX(uh, d, 64, float64, 64, uint16)
452 VFP_CONV_FIX(ul, d, 64, float64, 64, uint32)
453 VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64)
454 VFP_CONV_FIX(sh, s, 32, float32, 32, int16)
455 VFP_CONV_FIX(sl, s, 32, float32, 32, int32)
456 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64)
457 VFP_CONV_FIX(uh, s, 32, float32, 32, uint16)
458 VFP_CONV_FIX(ul, s, 32, float32, 32, uint32)
459 VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64)
460 VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16)
461 VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32)
462 VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64)
463 VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16)
464 VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32)
465 VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64)
466
467 #undef VFP_CONV_FIX
468 #undef VFP_CONV_FIX_FLOAT
469 #undef VFP_CONV_FLOAT_FIX_ROUND
470 #undef VFP_CONV_FIX_A64
471
472 /* Set the current fp rounding mode and return the old one.
473 * The argument is a softfloat float_round_ value.
474 */
HELPER(set_rmode)475 uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
476 {
477 float_status *fp_status = fpstp;
478
479 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
480 set_float_rounding_mode(rmode, fp_status);
481
482 return prev_rmode;
483 }
484
485 /* Half precision conversions. */
HELPER(vfp_fcvt_f16_to_f32)486 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
487 {
488 /* Squash FZ16 to 0 for the duration of conversion. In this case,
489 * it would affect flushing input denormals.
490 */
491 float_status *fpst = fpstp;
492 bool save = get_flush_inputs_to_zero(fpst);
493 set_flush_inputs_to_zero(false, fpst);
494 float32 r = float16_to_float32(a, !ahp_mode, fpst);
495 set_flush_inputs_to_zero(save, fpst);
496 return r;
497 }
498
HELPER(vfp_fcvt_f32_to_f16)499 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
500 {
501 /* Squash FZ16 to 0 for the duration of conversion. In this case,
502 * it would affect flushing output denormals.
503 */
504 float_status *fpst = fpstp;
505 bool save = get_flush_to_zero(fpst);
506 set_flush_to_zero(false, fpst);
507 float16 r = float32_to_float16(a, !ahp_mode, fpst);
508 set_flush_to_zero(save, fpst);
509 return r;
510 }
511
HELPER(vfp_fcvt_f16_to_f64)512 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
513 {
514 /* Squash FZ16 to 0 for the duration of conversion. In this case,
515 * it would affect flushing input denormals.
516 */
517 float_status *fpst = fpstp;
518 bool save = get_flush_inputs_to_zero(fpst);
519 set_flush_inputs_to_zero(false, fpst);
520 float64 r = float16_to_float64(a, !ahp_mode, fpst);
521 set_flush_inputs_to_zero(save, fpst);
522 return r;
523 }
524
HELPER(vfp_fcvt_f64_to_f16)525 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
526 {
527 /* Squash FZ16 to 0 for the duration of conversion. In this case,
528 * it would affect flushing output denormals.
529 */
530 float_status *fpst = fpstp;
531 bool save = get_flush_to_zero(fpst);
532 set_flush_to_zero(false, fpst);
533 float16 r = float64_to_float16(a, !ahp_mode, fpst);
534 set_flush_to_zero(save, fpst);
535 return r;
536 }
537
538 /* NEON helpers. */
539
540 /* Constants 256 and 512 are used in some helpers; we avoid relying on
541 * int->float conversions at run-time. */
542 #define float64_256 make_float64(0x4070000000000000LL)
543 #define float64_512 make_float64(0x4080000000000000LL)
544 #define float16_maxnorm make_float16(0x7bff)
545 #define float32_maxnorm make_float32(0x7f7fffff)
546 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
547
548 /* Reciprocal functions
549 *
550 * The algorithm that must be used to calculate the estimate
551 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
552 */
553
554 /* See RecipEstimate()
555 *
556 * input is a 9 bit fixed point number
557 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
558 * result range 256 .. 511 for a number from 1.0 to 511/256.
559 */
560
recip_estimate(int input)561 static int recip_estimate(int input)
562 {
563 int a, b, r;
564 assert(256 <= input && input < 512);
565 a = (input * 2) + 1;
566 b = (1 << 19) / a;
567 r = (b + 1) >> 1;
568 assert(256 <= r && r < 512);
569 return r;
570 }
571
572 /*
573 * Common wrapper to call recip_estimate
574 *
575 * The parameters are exponent and 64 bit fraction (without implicit
576 * bit) where the binary point is nominally at bit 52. Returns a
577 * float64 which can then be rounded to the appropriate size by the
578 * callee.
579 */
580
call_recip_estimate(int * exp,int exp_off,uint64_t frac)581 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
582 {
583 uint32_t scaled, estimate;
584 uint64_t result_frac;
585 int result_exp;
586
587 /* Handle sub-normals */
588 if (*exp == 0) {
589 if (extract64(frac, 51, 1) == 0) {
590 *exp = -1;
591 frac <<= 2;
592 } else {
593 frac <<= 1;
594 }
595 }
596
597 /* scaled = UInt('1':fraction<51:44>) */
598 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
599 estimate = recip_estimate(scaled);
600
601 result_exp = exp_off - *exp;
602 result_frac = deposit64(0, 44, 8, estimate);
603 if (result_exp == 0) {
604 result_frac = deposit64(result_frac >> 1, 51, 1, 1);
605 } else if (result_exp == -1) {
606 result_frac = deposit64(result_frac >> 2, 50, 2, 1);
607 result_exp = 0;
608 }
609
610 *exp = result_exp;
611
612 return result_frac;
613 }
614
round_to_inf(float_status * fpst,bool sign_bit)615 static bool round_to_inf(float_status *fpst, bool sign_bit)
616 {
617 switch (fpst->float_rounding_mode) {
618 case float_round_nearest_even: /* Round to Nearest */
619 return true;
620 case float_round_up: /* Round to +Inf */
621 return !sign_bit;
622 case float_round_down: /* Round to -Inf */
623 return sign_bit;
624 case float_round_to_zero: /* Round to Zero */
625 return false;
626 default:
627 g_assert_not_reached();
628 }
629 }
630
HELPER(recpe_f16)631 uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
632 {
633 float_status *fpst = fpstp;
634 float16 f16 = float16_squash_input_denormal(input, fpst);
635 uint32_t f16_val = float16_val(f16);
636 uint32_t f16_sign = float16_is_neg(f16);
637 int f16_exp = extract32(f16_val, 10, 5);
638 uint32_t f16_frac = extract32(f16_val, 0, 10);
639 uint64_t f64_frac;
640
641 if (float16_is_any_nan(f16)) {
642 float16 nan = f16;
643 if (float16_is_signaling_nan(f16, fpst)) {
644 float_raise(float_flag_invalid, fpst);
645 if (!fpst->default_nan_mode) {
646 nan = float16_silence_nan(f16, fpst);
647 }
648 }
649 if (fpst->default_nan_mode) {
650 nan = float16_default_nan(fpst);
651 }
652 return nan;
653 } else if (float16_is_infinity(f16)) {
654 return float16_set_sign(float16_zero, float16_is_neg(f16));
655 } else if (float16_is_zero(f16)) {
656 float_raise(float_flag_divbyzero, fpst);
657 return float16_set_sign(float16_infinity, float16_is_neg(f16));
658 } else if (float16_abs(f16) < (1 << 8)) {
659 /* Abs(value) < 2.0^-16 */
660 float_raise(float_flag_overflow | float_flag_inexact, fpst);
661 if (round_to_inf(fpst, f16_sign)) {
662 return float16_set_sign(float16_infinity, f16_sign);
663 } else {
664 return float16_set_sign(float16_maxnorm, f16_sign);
665 }
666 } else if (f16_exp >= 29 && fpst->flush_to_zero) {
667 float_raise(float_flag_underflow, fpst);
668 return float16_set_sign(float16_zero, float16_is_neg(f16));
669 }
670
671 f64_frac = call_recip_estimate(&f16_exp, 29,
672 ((uint64_t) f16_frac) << (52 - 10));
673
674 /* result = sign : result_exp<4:0> : fraction<51:42> */
675 f16_val = deposit32(0, 15, 1, f16_sign);
676 f16_val = deposit32(f16_val, 10, 5, f16_exp);
677 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
678 return make_float16(f16_val);
679 }
680
HELPER(recpe_f32)681 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
682 {
683 float_status *fpst = fpstp;
684 float32 f32 = float32_squash_input_denormal(input, fpst);
685 uint32_t f32_val = float32_val(f32);
686 bool f32_sign = float32_is_neg(f32);
687 int f32_exp = extract32(f32_val, 23, 8);
688 uint32_t f32_frac = extract32(f32_val, 0, 23);
689 uint64_t f64_frac;
690
691 if (float32_is_any_nan(f32)) {
692 float32 nan = f32;
693 if (float32_is_signaling_nan(f32, fpst)) {
694 float_raise(float_flag_invalid, fpst);
695 if (!fpst->default_nan_mode) {
696 nan = float32_silence_nan(f32, fpst);
697 }
698 }
699 if (fpst->default_nan_mode) {
700 nan = float32_default_nan(fpst);
701 }
702 return nan;
703 } else if (float32_is_infinity(f32)) {
704 return float32_set_sign(float32_zero, float32_is_neg(f32));
705 } else if (float32_is_zero(f32)) {
706 float_raise(float_flag_divbyzero, fpst);
707 return float32_set_sign(float32_infinity, float32_is_neg(f32));
708 } else if (float32_abs(f32) < (1ULL << 21)) {
709 /* Abs(value) < 2.0^-128 */
710 float_raise(float_flag_overflow | float_flag_inexact, fpst);
711 if (round_to_inf(fpst, f32_sign)) {
712 return float32_set_sign(float32_infinity, f32_sign);
713 } else {
714 return float32_set_sign(float32_maxnorm, f32_sign);
715 }
716 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
717 float_raise(float_flag_underflow, fpst);
718 return float32_set_sign(float32_zero, float32_is_neg(f32));
719 }
720
721 f64_frac = call_recip_estimate(&f32_exp, 253,
722 ((uint64_t) f32_frac) << (52 - 23));
723
724 /* result = sign : result_exp<7:0> : fraction<51:29> */
725 f32_val = deposit32(0, 31, 1, f32_sign);
726 f32_val = deposit32(f32_val, 23, 8, f32_exp);
727 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
728 return make_float32(f32_val);
729 }
730
HELPER(recpe_f64)731 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
732 {
733 float_status *fpst = fpstp;
734 float64 f64 = float64_squash_input_denormal(input, fpst);
735 uint64_t f64_val = float64_val(f64);
736 bool f64_sign = float64_is_neg(f64);
737 int f64_exp = extract64(f64_val, 52, 11);
738 uint64_t f64_frac = extract64(f64_val, 0, 52);
739
740 /* Deal with any special cases */
741 if (float64_is_any_nan(f64)) {
742 float64 nan = f64;
743 if (float64_is_signaling_nan(f64, fpst)) {
744 float_raise(float_flag_invalid, fpst);
745 if (!fpst->default_nan_mode) {
746 nan = float64_silence_nan(f64, fpst);
747 }
748 }
749 if (fpst->default_nan_mode) {
750 nan = float64_default_nan(fpst);
751 }
752 return nan;
753 } else if (float64_is_infinity(f64)) {
754 return float64_set_sign(float64_zero, float64_is_neg(f64));
755 } else if (float64_is_zero(f64)) {
756 float_raise(float_flag_divbyzero, fpst);
757 return float64_set_sign(float64_infinity, float64_is_neg(f64));
758 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
759 /* Abs(value) < 2.0^-1024 */
760 float_raise(float_flag_overflow | float_flag_inexact, fpst);
761 if (round_to_inf(fpst, f64_sign)) {
762 return float64_set_sign(float64_infinity, f64_sign);
763 } else {
764 return float64_set_sign(float64_maxnorm, f64_sign);
765 }
766 } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
767 float_raise(float_flag_underflow, fpst);
768 return float64_set_sign(float64_zero, float64_is_neg(f64));
769 }
770
771 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
772
773 /* result = sign : result_exp<10:0> : fraction<51:0>; */
774 f64_val = deposit64(0, 63, 1, f64_sign);
775 f64_val = deposit64(f64_val, 52, 11, f64_exp);
776 f64_val = deposit64(f64_val, 0, 52, f64_frac);
777 return make_float64(f64_val);
778 }
779
780 /* The algorithm that must be used to calculate the estimate
781 * is specified by the ARM ARM.
782 */
783
do_recip_sqrt_estimate(int a)784 static int do_recip_sqrt_estimate(int a)
785 {
786 int b, estimate;
787
788 assert(128 <= a && a < 512);
789 if (a < 256) {
790 a = a * 2 + 1;
791 } else {
792 a = (a >> 1) << 1;
793 a = (a + 1) * 2;
794 }
795 b = 512;
796 while (a * (b + 1) * (b + 1) < (1 << 28)) {
797 b += 1;
798 }
799 estimate = (b + 1) / 2;
800 assert(256 <= estimate && estimate < 512);
801
802 return estimate;
803 }
804
805
recip_sqrt_estimate(int * exp,int exp_off,uint64_t frac)806 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
807 {
808 int estimate;
809 uint32_t scaled;
810
811 if (*exp == 0) {
812 while (extract64(frac, 51, 1) == 0) {
813 frac = frac << 1;
814 *exp -= 1;
815 }
816 frac = extract64(frac, 0, 51) << 1;
817 }
818
819 if (*exp & 1) {
820 /* scaled = UInt('01':fraction<51:45>) */
821 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
822 } else {
823 /* scaled = UInt('1':fraction<51:44>) */
824 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
825 }
826 estimate = do_recip_sqrt_estimate(scaled);
827
828 *exp = (exp_off - *exp) / 2;
829 return extract64(estimate, 0, 8) << 44;
830 }
831
HELPER(rsqrte_f16)832 uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
833 {
834 float_status *s = fpstp;
835 float16 f16 = float16_squash_input_denormal(input, s);
836 uint16_t val = float16_val(f16);
837 bool f16_sign = float16_is_neg(f16);
838 int f16_exp = extract32(val, 10, 5);
839 uint16_t f16_frac = extract32(val, 0, 10);
840 uint64_t f64_frac;
841
842 if (float16_is_any_nan(f16)) {
843 float16 nan = f16;
844 if (float16_is_signaling_nan(f16, s)) {
845 float_raise(float_flag_invalid, s);
846 if (!s->default_nan_mode) {
847 nan = float16_silence_nan(f16, fpstp);
848 }
849 }
850 if (s->default_nan_mode) {
851 nan = float16_default_nan(s);
852 }
853 return nan;
854 } else if (float16_is_zero(f16)) {
855 float_raise(float_flag_divbyzero, s);
856 return float16_set_sign(float16_infinity, f16_sign);
857 } else if (f16_sign) {
858 float_raise(float_flag_invalid, s);
859 return float16_default_nan(s);
860 } else if (float16_is_infinity(f16)) {
861 return float16_zero;
862 }
863
864 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
865 * preserving the parity of the exponent. */
866
867 f64_frac = ((uint64_t) f16_frac) << (52 - 10);
868
869 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
870
871 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
872 val = deposit32(0, 15, 1, f16_sign);
873 val = deposit32(val, 10, 5, f16_exp);
874 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
875 return make_float16(val);
876 }
877
HELPER(rsqrte_f32)878 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
879 {
880 float_status *s = fpstp;
881 float32 f32 = float32_squash_input_denormal(input, s);
882 uint32_t val = float32_val(f32);
883 uint32_t f32_sign = float32_is_neg(f32);
884 int f32_exp = extract32(val, 23, 8);
885 uint32_t f32_frac = extract32(val, 0, 23);
886 uint64_t f64_frac;
887
888 if (float32_is_any_nan(f32)) {
889 float32 nan = f32;
890 if (float32_is_signaling_nan(f32, s)) {
891 float_raise(float_flag_invalid, s);
892 if (!s->default_nan_mode) {
893 nan = float32_silence_nan(f32, fpstp);
894 }
895 }
896 if (s->default_nan_mode) {
897 nan = float32_default_nan(s);
898 }
899 return nan;
900 } else if (float32_is_zero(f32)) {
901 float_raise(float_flag_divbyzero, s);
902 return float32_set_sign(float32_infinity, float32_is_neg(f32));
903 } else if (float32_is_neg(f32)) {
904 float_raise(float_flag_invalid, s);
905 return float32_default_nan(s);
906 } else if (float32_is_infinity(f32)) {
907 return float32_zero;
908 }
909
910 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
911 * preserving the parity of the exponent. */
912
913 f64_frac = ((uint64_t) f32_frac) << 29;
914
915 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
916
917 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
918 val = deposit32(0, 31, 1, f32_sign);
919 val = deposit32(val, 23, 8, f32_exp);
920 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
921 return make_float32(val);
922 }
923
HELPER(rsqrte_f64)924 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
925 {
926 float_status *s = fpstp;
927 float64 f64 = float64_squash_input_denormal(input, s);
928 uint64_t val = float64_val(f64);
929 bool f64_sign = float64_is_neg(f64);
930 int f64_exp = extract64(val, 52, 11);
931 uint64_t f64_frac = extract64(val, 0, 52);
932
933 if (float64_is_any_nan(f64)) {
934 float64 nan = f64;
935 if (float64_is_signaling_nan(f64, s)) {
936 float_raise(float_flag_invalid, s);
937 if (!s->default_nan_mode) {
938 nan = float64_silence_nan(f64, fpstp);
939 }
940 }
941 if (s->default_nan_mode) {
942 nan = float64_default_nan(s);
943 }
944 return nan;
945 } else if (float64_is_zero(f64)) {
946 float_raise(float_flag_divbyzero, s);
947 return float64_set_sign(float64_infinity, float64_is_neg(f64));
948 } else if (float64_is_neg(f64)) {
949 float_raise(float_flag_invalid, s);
950 return float64_default_nan(s);
951 } else if (float64_is_infinity(f64)) {
952 return float64_zero;
953 }
954
955 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
956
957 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
958 val = deposit64(0, 61, 1, f64_sign);
959 val = deposit64(val, 52, 11, f64_exp);
960 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
961 return make_float64(val);
962 }
963
HELPER(recpe_u32)964 uint32_t HELPER(recpe_u32)(uint32_t a)
965 {
966 int input, estimate;
967
968 if ((a & 0x80000000) == 0) {
969 return 0xffffffff;
970 }
971
972 input = extract32(a, 23, 9);
973 estimate = recip_estimate(input);
974
975 return deposit32(0, (32 - 9), 9, estimate);
976 }
977
HELPER(rsqrte_u32)978 uint32_t HELPER(rsqrte_u32)(uint32_t a)
979 {
980 int estimate;
981
982 if ((a & 0xc0000000) == 0) {
983 return 0xffffffff;
984 }
985
986 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
987
988 return deposit32(0, 23, 9, estimate);
989 }
990
991 /* VFPv4 fused multiply-accumulate */
VFP_HELPER(muladd,h)992 dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b,
993 dh_ctype_f16 c, void *fpstp)
994 {
995 float_status *fpst = fpstp;
996 return float16_muladd(a, b, c, 0, fpst);
997 }
998
VFP_HELPER(muladd,s)999 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
1000 {
1001 float_status *fpst = fpstp;
1002 return float32_muladd(a, b, c, 0, fpst);
1003 }
1004
VFP_HELPER(muladd,d)1005 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
1006 {
1007 float_status *fpst = fpstp;
1008 return float64_muladd(a, b, c, 0, fpst);
1009 }
1010
1011 /* ARMv8 round to integral */
HELPER(rinth_exact)1012 dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status)
1013 {
1014 return float16_round_to_int(x, fp_status);
1015 }
1016
HELPER(rints_exact)1017 float32 HELPER(rints_exact)(float32 x, void *fp_status)
1018 {
1019 return float32_round_to_int(x, fp_status);
1020 }
1021
HELPER(rintd_exact)1022 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
1023 {
1024 return float64_round_to_int(x, fp_status);
1025 }
1026
HELPER(rinth)1027 dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
1028 {
1029 int old_flags = get_float_exception_flags(fp_status), new_flags;
1030 float16 ret;
1031
1032 ret = float16_round_to_int(x, fp_status);
1033
1034 /* Suppress any inexact exceptions the conversion produced */
1035 if (!(old_flags & float_flag_inexact)) {
1036 new_flags = get_float_exception_flags(fp_status);
1037 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1038 }
1039
1040 return ret;
1041 }
1042
HELPER(rints)1043 float32 HELPER(rints)(float32 x, void *fp_status)
1044 {
1045 int old_flags = get_float_exception_flags(fp_status), new_flags;
1046 float32 ret;
1047
1048 ret = float32_round_to_int(x, fp_status);
1049
1050 /* Suppress any inexact exceptions the conversion produced */
1051 if (!(old_flags & float_flag_inexact)) {
1052 new_flags = get_float_exception_flags(fp_status);
1053 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1054 }
1055
1056 return ret;
1057 }
1058
HELPER(rintd)1059 float64 HELPER(rintd)(float64 x, void *fp_status)
1060 {
1061 int old_flags = get_float_exception_flags(fp_status), new_flags;
1062 float64 ret;
1063
1064 ret = float64_round_to_int(x, fp_status);
1065
1066 new_flags = get_float_exception_flags(fp_status);
1067
1068 /* Suppress any inexact exceptions the conversion produced */
1069 if (!(old_flags & float_flag_inexact)) {
1070 new_flags = get_float_exception_flags(fp_status);
1071 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1072 }
1073
1074 return ret;
1075 }
1076
1077 /* Convert ARM rounding mode to softfloat */
1078 const FloatRoundMode arm_rmode_to_sf_map[] = {
1079 [FPROUNDING_TIEEVEN] = float_round_nearest_even,
1080 [FPROUNDING_POSINF] = float_round_up,
1081 [FPROUNDING_NEGINF] = float_round_down,
1082 [FPROUNDING_ZERO] = float_round_to_zero,
1083 [FPROUNDING_TIEAWAY] = float_round_ties_away,
1084 [FPROUNDING_ODD] = float_round_to_odd,
1085 };
1086
1087 /*
1088 * Implement float64 to int32_t conversion without saturation;
1089 * the result is supplied modulo 2^32.
1090 */
HELPER(fjcvtzs)1091 uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
1092 {
1093 float_status *status = vstatus;
1094 uint32_t inexact, frac;
1095 uint32_t e_old, e_new;
1096
1097 e_old = get_float_exception_flags(status);
1098 set_float_exception_flags(0, status);
1099 frac = float64_to_int32_modulo(value, float_round_to_zero, status);
1100 e_new = get_float_exception_flags(status);
1101 set_float_exception_flags(e_old | e_new, status);
1102
1103 if (value == float64_chs(float64_zero)) {
1104 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1105 inexact = 1;
1106 } else {
1107 /* Normal inexact or overflow or NaN */
1108 inexact = e_new & (float_flag_inexact | float_flag_invalid);
1109 }
1110
1111 /* Pack the result and the env->ZF representation of Z together. */
1112 return deposit64(frac, 32, 32, inexact);
1113 }
1114
HELPER(vjcvt)1115 uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
1116 {
1117 uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status);
1118 uint32_t result = pair;
1119 uint32_t z = (pair >> 32) == 0;
1120
1121 /* Store Z, clear NCV, in FPSCR.NZCV. */
1122 env->vfp.xregs[ARM_VFP_FPSCR]
1123 = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z);
1124
1125 return result;
1126 }
1127
1128 /* Round a float32 to an integer that fits in int32_t or int64_t. */
frint_s(float32 f,float_status * fpst,int intsize)1129 static float32 frint_s(float32 f, float_status *fpst, int intsize)
1130 {
1131 int old_flags = get_float_exception_flags(fpst);
1132 uint32_t exp = extract32(f, 23, 8);
1133
1134 if (unlikely(exp == 0xff)) {
1135 /* NaN or Inf. */
1136 goto overflow;
1137 }
1138
1139 /* Round and re-extract the exponent. */
1140 f = float32_round_to_int(f, fpst);
1141 exp = extract32(f, 23, 8);
1142
1143 /* Validate the range of the result. */
1144 if (exp < 126 + intsize) {
1145 /* abs(F) <= INT{N}_MAX */
1146 return f;
1147 }
1148 if (exp == 126 + intsize) {
1149 uint32_t sign = extract32(f, 31, 1);
1150 uint32_t frac = extract32(f, 0, 23);
1151 if (sign && frac == 0) {
1152 /* F == INT{N}_MIN */
1153 return f;
1154 }
1155 }
1156
1157 overflow:
1158 /*
1159 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1160 * inexact exception float32_round_to_int may have raised.
1161 */
1162 set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1163 return (0x100u + 126u + intsize) << 23;
1164 }
1165
HELPER(frint32_s)1166 float32 HELPER(frint32_s)(float32 f, void *fpst)
1167 {
1168 return frint_s(f, fpst, 32);
1169 }
1170
HELPER(frint64_s)1171 float32 HELPER(frint64_s)(float32 f, void *fpst)
1172 {
1173 return frint_s(f, fpst, 64);
1174 }
1175
1176 /* Round a float64 to an integer that fits in int32_t or int64_t. */
frint_d(float64 f,float_status * fpst,int intsize)1177 static float64 frint_d(float64 f, float_status *fpst, int intsize)
1178 {
1179 int old_flags = get_float_exception_flags(fpst);
1180 uint32_t exp = extract64(f, 52, 11);
1181
1182 if (unlikely(exp == 0x7ff)) {
1183 /* NaN or Inf. */
1184 goto overflow;
1185 }
1186
1187 /* Round and re-extract the exponent. */
1188 f = float64_round_to_int(f, fpst);
1189 exp = extract64(f, 52, 11);
1190
1191 /* Validate the range of the result. */
1192 if (exp < 1022 + intsize) {
1193 /* abs(F) <= INT{N}_MAX */
1194 return f;
1195 }
1196 if (exp == 1022 + intsize) {
1197 uint64_t sign = extract64(f, 63, 1);
1198 uint64_t frac = extract64(f, 0, 52);
1199 if (sign && frac == 0) {
1200 /* F == INT{N}_MIN */
1201 return f;
1202 }
1203 }
1204
1205 overflow:
1206 /*
1207 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1208 * inexact exception float64_round_to_int may have raised.
1209 */
1210 set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1211 return (uint64_t)(0x800 + 1022 + intsize) << 52;
1212 }
1213
HELPER(frint32_d)1214 float64 HELPER(frint32_d)(float64 f, void *fpst)
1215 {
1216 return frint_d(f, fpst, 32);
1217 }
1218
HELPER(frint64_d)1219 float64 HELPER(frint64_d)(float64 f, void *fpst)
1220 {
1221 return frint_d(f, fpst, 64);
1222 }
1223
HELPER(check_hcr_el2_trap)1224 void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg)
1225 {
1226 uint32_t syndrome;
1227
1228 switch (reg) {
1229 case ARM_VFP_MVFR0:
1230 case ARM_VFP_MVFR1:
1231 case ARM_VFP_MVFR2:
1232 if (!(arm_hcr_el2_eff(env) & HCR_TID3)) {
1233 return;
1234 }
1235 break;
1236 case ARM_VFP_FPSID:
1237 if (!(arm_hcr_el2_eff(env) & HCR_TID0)) {
1238 return;
1239 }
1240 break;
1241 default:
1242 g_assert_not_reached();
1243 }
1244
1245 syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT)
1246 | ARM_EL_IL
1247 | (1 << 24) | (0xe << 20) | (7 << 14)
1248 | (reg << 10) | (rt << 5) | 1);
1249
1250 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
1251 }
1252
1253 #endif
1254