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Searched refs:fpr (Results 1 – 25 of 45) sorted by relevance

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/qemu/target/sparc/
H A Dmonitor.c134 { "f32", offsetof(CPUSPARCState, fpr[16]) },
135 { "f34", offsetof(CPUSPARCState, fpr[17]) },
136 { "f36", offsetof(CPUSPARCState, fpr[18]) },
137 { "f38", offsetof(CPUSPARCState, fpr[19]) },
138 { "f40", offsetof(CPUSPARCState, fpr[20]) },
139 { "f42", offsetof(CPUSPARCState, fpr[21]) },
140 { "f44", offsetof(CPUSPARCState, fpr[22]) },
141 { "f46", offsetof(CPUSPARCState, fpr[23]) },
142 { "f48", offsetof(CPUSPARCState, fpr[24]) },
143 { "f50", offsetof(CPUSPARCState, fpr[25]) },
[all …]
H A Dgdbstub.c46 return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower); in sparc_cpu_gdb_read_register()
48 return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper); in sparc_cpu_gdb_read_register()
76 return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower); in sparc_cpu_gdb_read_register()
78 return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper); in sparc_cpu_gdb_read_register()
83 return gdb_get_reg64(mem_buf, env->fpr[(n - 32) / 2].ll); in sparc_cpu_gdb_read_register()
132 env->fpr[(n - 32) / 2].l.lower = tmp; in sparc_cpu_gdb_write_register()
134 env->fpr[(n - 32) / 2].l.upper = tmp; in sparc_cpu_gdb_write_register()
170 env->fpr[(n - 32) / 2].l.lower = tmp; in sparc_cpu_gdb_write_register()
172 env->fpr[(n - 32) / 2].l.upper = tmp; in sparc_cpu_gdb_write_register()
177 env->fpr[(n - 32) / 2].ll = tmp; in sparc_cpu_gdb_write_register()
/qemu/target/mips/tcg/
H A Dmsa_helper.c100 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); in helper_msa_nloc_b()
101 wr_t *pws = &(env->active_fpu.fpr[ws].wr); in helper_msa_nloc_b()
123 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); in helper_msa_nloc_h()
124 wr_t *pws = &(env->active_fpu.fpr[ws].wr); in helper_msa_nloc_h()
138 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); in helper_msa_nloc_w()
139 wr_t *pws = &(env->active_fpu.fpr[ws].wr); in helper_msa_nloc_w()
149 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); in helper_msa_nloc_d()
150 wr_t *pws = &(env->active_fpu.fpr[ws].wr); in helper_msa_nloc_d()
158 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); in helper_msa_nlzc_b()
159 wr_t *pws = &(env->active_fpu.fpr[ws].wr); in helper_msa_nlzc_b()
[all …]
/qemu/linux-user/mips/
H A Dtarget_prctl.h58 fpr_t *fpr = env->active_fpu.fpr; in do_prctl_set_fp_mode() local
61 fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX]; in do_prctl_set_fp_mode()
63 fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX]; in do_prctl_set_fp_mode()
H A Dsignal.c135 __put_user(regs->active_fpu.fpr[i].d, &sc->sc_fpregs[i]); in setup_sigcontext()
166 __get_user(regs->active_fpu.fpr[i].d, &sc->sc_fpregs[i]); in restore_sigcontext()
/qemu/tests/tcg/riscv64/
H A Dtest-fcvtmod.c77 double fpr; in do_fmv_d_x() local
78 __asm__ __volatile__("fmv.d.x %0, %1" : "=f"(fpr) : "r"(inp)); in do_fmv_d_x()
79 return fpr; in do_fmv_d_x()
85 double fpr = do_fmv_d_x(inp); in do_fcvt_w_d() local
89 __asm__ __volatile__("fcvt.w.d %0, %1, rtz" : "=r"(ret) : "f"(fpr)); in do_fcvt_w_d()
99 double fpr = do_fmv_d_x(inp); in do_fcvtmod_w_d() local
104 asm(".insn r 0x53, 0x1, 0x61, %0, %1, f8" : "=r"(ret) : "f"(fpr)); in do_fcvtmod_w_d()
308 double fpr = do_fmv_d_x(t->inp_lu); in run_fcvtmod_tests() local
309 printf("inp_lu: 0x%016lx == %lf\n", t->inp_lu, fpr); in run_fcvtmod_tests()
/qemu/linux-user/loongarch64/
H A Dsignal.c179 __put_user(env->fpr[i].vreg.UD(0), &lasx_ctx->regs[4 * i]); in setup_sigframe()
180 __put_user(env->fpr[i].vreg.UD(1), &lasx_ctx->regs[4 * i + 1]); in setup_sigframe()
181 __put_user(env->fpr[i].vreg.UD(2), &lasx_ctx->regs[4 * i + 2]); in setup_sigframe()
182 __put_user(env->fpr[i].vreg.UD(3), &lasx_ctx->regs[4 * i + 3]); in setup_sigframe()
196 __put_user(env->fpr[i].vreg.UD(0), &lsx_ctx->regs[2 * i]); in setup_sigframe()
197 __put_user(env->fpr[i].vreg.UD(1), &lsx_ctx->regs[2 * i + 1]); in setup_sigframe()
211 __put_user(env->fpr[i].vreg.UD(0), &fpu_ctx->regs[i]); in setup_sigframe()
295 __get_user(env->fpr[i].vreg.UD(0), &lasx_ctx->regs[4 * i]); in restore_sigframe()
309 __get_user(env->fpr[i].vreg.UD(0), &lsx_ctx->regs[2 * i]); in restore_sigframe()
310 __get_user(env->fpr[i].vreg.UD(1), &lsx_ctx->regs[2 * i + 1]); in restore_sigframe()
[all …]
/qemu/target/loongarch/kvm/
H A Dkvm.c438 env->fpr[i].vreg.UD[0] = fpu.fpr[i].val64[0]; in kvm_loongarch_get_regs_fp()
439 env->fpr[i].vreg.UD[1] = fpu.fpr[i].val64[1]; in kvm_loongarch_get_regs_fp()
440 env->fpr[i].vreg.UD[2] = fpu.fpr[i].val64[2]; in kvm_loongarch_get_regs_fp()
441 env->fpr[i].vreg.UD[3] = fpu.fpr[i].val64[3]; in kvm_loongarch_get_regs_fp()
460 fpu.fpr[i].val64[0] = env->fpr[i].vreg.UD[0]; in kvm_loongarch_put_regs_fp()
461 fpu.fpr[i].val64[1] = env->fpr[i].vreg.UD[1]; in kvm_loongarch_put_regs_fp()
462 fpu.fpr[i].val64[2] = env->fpr[i].vreg.UD[2]; in kvm_loongarch_put_regs_fp()
463 fpu.fpr[i].val64[3] = env->fpr[i].vreg.UD[3]; in kvm_loongarch_put_regs_fp()
/qemu/linux-user/riscv/
H A Dsignal.c37 uint64_t fpr[32]; member
41 QEMU_BUILD_BUG_ON(offsetof(struct target_sigcontext, fpr) != offsetof_freg0);
90 __put_user(env->fpr[i], &sc->fpr[i]); in setup_sigcontext()
157 __get_user(env->fpr[i], &sc->fpr[i]); in restore_sigcontext()
/qemu/target/mips/
H A Dgdbstub.c42 env->active_fpu.fpr[n - 38].d); in mips_cpu_gdb_read_register()
45 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); in mips_cpu_gdb_read_register()
101 env->active_fpu.fpr[n - 38].d = tmp; in mips_cpu_gdb_write_register()
103 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; in mips_cpu_gdb_write_register()
H A Dcpu.c45 static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) in fpu_dump_fpr() argument
49 fpr->w[FP_ENDIAN_IDX], fpr->d, in fpu_dump_fpr()
50 (double)fpr->fd, in fpu_dump_fpr()
51 (double)fpr->fs[FP_ENDIAN_IDX], in fpu_dump_fpr()
52 (double)fpr->fs[!FP_ENDIAN_IDX]); in fpu_dump_fpr()
56 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX]; in fpu_dump_fpr()
57 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX]; in fpu_dump_fpr()
77 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); in fpu_dump_state()
H A Dkvm.c621 &env->active_fpu.fpr[i].d); in kvm_mips_put_fpu_registers()
624 &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); in kvm_mips_put_fpu_registers()
656 env->active_fpu.fpr[i].wr.d); in kvm_mips_put_fpu_registers()
700 &env->active_fpu.fpr[i].d); in kvm_mips_get_fpu_registers()
703 &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); in kvm_mips_get_fpu_registers()
735 env->active_fpu.fpr[i].wr.d); in kvm_mips_get_fpu_registers()
/qemu/target/loongarch/tcg/
H A Dtranslate.c37 return offsetof(CPULoongArchState, fpr[regno]); in vec_full_offset()
55 offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); in get_vreg64()
61 offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); in set_vreg64()
225 offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); in get_fpr()
232 offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); in set_fpr()
/qemu/target/arm/
H A Darch_dump.c192 uint32_t fpr; in aarch64_write_elf64_sve() local
218 fpr = cpu_to_dump32(s, vfp_get_fpsr(env)); in aarch64_write_elf64_sve()
219 memcpy(&buf[sve_fpsr_offset(vq)], &fpr, sizeof(uint32_t)); in aarch64_write_elf64_sve()
221 fpr = cpu_to_dump32(s, vfp_get_fpcr(env)); in aarch64_write_elf64_sve()
222 memcpy(&buf[sve_fpcr_offset(vq)], &fpr, sizeof(uint32_t)); in aarch64_write_elf64_sve()
H A Dkvm.c2053 uint32_t fpr; in kvm_arch_put_registers() local
2141 fpr = vfp_get_fpsr(env); in kvm_arch_put_registers()
2142 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); in kvm_arch_put_registers()
2147 fpr = vfp_get_fpcr(env); in kvm_arch_put_registers()
2148 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); in kvm_arch_put_registers()
2238 uint32_t fpr; in kvm_arch_get_registers() local
2325 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); in kvm_arch_get_registers()
2329 vfp_set_fpsr(env, fpr); in kvm_arch_get_registers()
2331 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); in kvm_arch_get_registers()
2335 vfp_set_fpcr(env, fpr); in kvm_arch_get_registers()
/qemu/target/ppc/
H A Darch_dump.c57 uint64_t fpr[32]; member
143 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); in ppc_write_elf_fpregset() local
144 fpregset->fpr[i] = cpu_to_dump64(s, *fpr); in ppc_write_elf_fpregset()
/qemu/target/loongarch/
H A Dgdbstub.c91 return gdb_get_reg64(mem_buf, env->fpr[n].vreg.D(0)); in loongarch_gdb_get_fpu()
107 env->fpr[n].vreg.D(0) = ldq_p(mem_buf); in loongarch_gdb_set_fpu()
H A Dmachine.c41 VMSTATE_FPU_REGS(env.fpr, LoongArchCPU, 0),
75 VMSTATE_LSXH_REGS(env.fpr, LoongArchCPU, 0),
108 VMSTATE_LASXH_REGS(env.fpr, LoongArchCPU, 0),
/qemu/linux-user/sparc/
H A Dsignal.c200 __put_user(env->fpr[i].ll, &fpu->si_double_regs[i]); in save_fpu()
207 __put_user(env->fpr[i].ll, &fpu->si_double_regs[i]); in save_fpu()
226 __get_user(env->fpr[i].ll, &fpu->si_double_regs[i]); in restore_fpu()
231 __get_user(env->fpr[i].ll, &fpu->si_double_regs[i]); in restore_fpu()
238 __get_user(env->fpr[i].ll, &fpu->si_double_regs[i]); in restore_fpu()
688 __get_user(env->fpr[i].ll, &(fpup->mcfpu_fregs.dregs[i])); in sparc64_set_context()
693 __get_user(env->fpr[i].ll, &(fpup->mcfpu_fregs.dregs[i])); in sparc64_set_context()
/qemu/target/riscv/
H A Dgdbstub.c118 return gdb_get_reg64(buf, env->fpr[n]); in riscv_gdb_get_fpu()
121 return gdb_get_reg32(buf, env->fpr[n]); in riscv_gdb_get_fpu()
133 env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */ in riscv_gdb_set_fpu()
/qemu/configs/targets/
H A Ds390x-linux-user.mak5 TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-v…
H A Ds390x-softmmu.mak5 TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-v…
/qemu/bsd-user/arm/
H A Dtarget_arch_reg.h40 target_fp_reg_t fpr[8]; member
/qemu/linux-headers/asm-loongarch/
H A Dkvm.h37 } fpr[32]; member
/qemu/linux-user/ppc/
H A Dsignal.c299 uint64_t *fpr = cpu_fpr_ptr(env, i); in save_user_regs() local
300 __put_user(*fpr, &frame->mc_fregs[i]); in save_user_regs()
407 uint64_t *fpr = cpu_fpr_ptr(env, i); in restore_user_regs() local
408 __get_user(*fpr, &frame->mc_fregs[i]); in restore_user_regs()

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