/qemu/target/arm/tcg/ |
H A D | translate-m-nocp.c | 330 TCGv_i32 fpscr; in gen_M_fp_sysreg_write() local 345 tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); in gen_M_fp_sysreg_write() 346 tcg_gen_or_i32(fpscr, fpscr, tmp); in gen_M_fp_sysreg_write() 474 TCGv_i32 control, sfpa, fpscr; in gen_M_fp_sysreg_read() local 495 fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read() 496 gen_helper_vfp_set_fpscr(tcg_env, fpscr); in gen_M_fp_sysreg_read() 502 TCGv_i32 control, sfpa, fpscr, fpdscr; in gen_M_fp_sysreg_read() local 530 fpscr = tcg_temp_new_i32(); in gen_M_fp_sysreg_read() 531 gen_helper_vfp_get_fpscr(fpscr, tcg_env); in gen_M_fp_sysreg_read() 542 fpdscr, fpscr); in gen_M_fp_sysreg_read() [all …]
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H A D | m_helper.c | 1144 uint32_t fpscr; in HELPER() local 1165 fpscr = cpu_ldl_data_ra(env, fptr + 0x40, ra); in HELPER() 1166 vfp_set_fpscr(env, fpscr); in HELPER() 1762 uint32_t fpscr; in do_v7m_exception_exit() local 1812 v7m_stack_read(cpu, &fpscr, frameptr + 0x60, mmu_idx); in do_v7m_exception_exit() 1814 vfp_set_fpscr(env, fpscr); in do_v7m_exception_exit()
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/qemu/target/ppc/ |
H A D | fpu_helper.c | 165 env->fpscr = (env->fpscr & ~FP_FPRF) | fprf; \ 177 env->fpscr |= FP_VX; in COMPUTE_FPRF() 179 env->fpscr |= FP_FX; in COMPUTE_FPRF() 260 env->fpscr |= FP_VX; in float_invalid_op_vxvc() 262 env->fpscr |= FP_FX; in float_invalid_op_vxvc() 393 target_ulong fpscr = env->fpscr; in do_fpscr_check_status() local 396 if ((fpscr & FP_OX) && (fpscr & FP_OE)) { in do_fpscr_check_status() 398 } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) { in do_fpscr_check_status() 400 } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) { in do_fpscr_check_status() 402 } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) { in do_fpscr_check_status() [all …]
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H A D | cpu.c | 199 switch (env->fpscr & FP_RN) { in fpscr_set_rounding_mode() 230 env->fpscr = val; in ppc_store_fpscr() 231 env->fp_status.rebias_overflow = (FP_OE & env->fpscr) ? true : false; in ppc_store_fpscr() 232 env->fp_status.rebias_underflow = (FP_UE & env->fpscr) ? true : false; in ppc_store_fpscr()
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H A D | dfp_helper.c | 74 switch ((fpscr & FP_DRN) >> FPSCR_DRN0) { in dfp_prepare_rounding_mode() 151 dfp_prepare_rounding_mode(&dfp->context, env->fpscr); in dfp_prepare_decimal64() 208 dfp->env->fpscr |= (flag | FP_FX); in dfp_set_FPSCR_flag() 209 if (dfp->env->fpscr & enabled) { in dfp_set_FPSCR_flag() 210 dfp->env->fpscr |= FP_FEX; in dfp_set_FPSCR_flag() 254 dfp->env->fpscr &= ~FP_FPRF; in dfp_set_FPRF_from_FRT_with_context() 255 dfp->env->fpscr |= (fprf << FPSCR_FPRF); in dfp_set_FPRF_from_FRT_with_context() 403 dfp->env->fpscr &= ~FP_FPCC; in dfp_set_FPCC_from_CRBF() 404 dfp->env->fpscr |= (dfp->crbf << FPSCR_FPCC); in dfp_set_FPCC_from_CRBF() 1154 if ((dfp->env->fpscr & FP_VE) == 0) { in dfp_invalid_op_vxcvi_64() [all …]
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H A D | arch_dump.c | 58 reg_t fpscr; member 146 fpregset->fpscr = cpu_to_dump_reg(s, cpu->env.fpscr); in ppc_write_elf_fpregset()
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H A D | ppc-qmp-cmds.c | 95 { "fpscr", offsetof(CPUPPCState, fpscr) },
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H A D | gdbstub.c | 196 gdb_get_reg64(buf, env->fpscr); in ppc_cpu_gdb_read_register_apple() 452 gdb_get_reg32(buf, env->fpscr); in gdb_get_float_reg()
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H A D | kvm.c | 629 uint64_t fpscr = env->fpscr; in kvm_put_fp() local 633 reg.addr = (uintptr_t)&fpscr; in kvm_put_fp() 695 uint64_t fpscr; in kvm_get_fp() local 699 reg.addr = (uintptr_t)&fpscr; in kvm_get_fp() 705 env->fpscr = fpscr; in kvm_get_fp()
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H A D | machine.c | 356 VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
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/qemu/tests/tcg/ppc64/ |
H A D | mffsce.c | 20 uint64_t frt, fpscr; in main() local 25 MFFS(fpscr); /* read the value that mffsce stored to cpu fpscr */ in main() 34 assert((fpscr & 0xff) == (test_value & 0x7)); in main()
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H A D | mtfsf.c | 28 uint64_t fpscr; in main() local 45 MFFS(fpscr); in main() 46 assert((fpscr & FP_FI) != 0); in main()
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/qemu/target/sh4/ |
H A D | op_helper.c | 207 env->fpscr = val & FPSCR_MASK; in helper_ld_fpscr() 223 env->fpscr &= ~FPSCR_CAUSE_MASK; in update_fpscr() 227 env->fpscr |= FPSCR_CAUSE_V; in update_fpscr() 230 env->fpscr |= FPSCR_CAUSE_Z; in update_fpscr() 233 env->fpscr |= FPSCR_CAUSE_O; in update_fpscr() 236 env->fpscr |= FPSCR_CAUSE_U; in update_fpscr() 239 env->fpscr |= FPSCR_CAUSE_I; in update_fpscr() 243 env->fpscr |= (env->fpscr & FPSCR_CAUSE_MASK) in update_fpscr() 247 cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; in update_fpscr() 248 enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT; in update_fpscr()
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H A D | gdbstub.c | 57 return gdb_get_regl(mem_buf, env->fpscr); in superh_cpu_gdb_read_register() 59 if (env->fpscr & FPSCR_FR) { in superh_cpu_gdb_read_register() 116 env->fpscr = ldl_p(mem_buf); in superh_cpu_gdb_write_register() 119 if (env->fpscr & FPSCR_FR) { in superh_cpu_gdb_write_register()
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H A D | cpu.c | 120 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ in superh_cpu_reset_hold() 125 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ in superh_cpu_reset_hold()
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H A D | cpu.h | 159 uint32_t fpscr; /* floating point status/control register */ member 390 | (env->fpscr & TB_FLAG_FPSCR_MASK) in cpu_get_tb_cpu_state()
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/qemu/target/ppc/translate/ |
H A D | fp-impl.c.inc | 490 TCGv_i64 fpscr = tcg_temp_new_i64(); 493 tcg_gen_extu_tl_i64(fpscr, cpu_fpscr); 494 tcg_gen_andi_i64(fpscr_masked, fpscr, mask); 497 return fpscr; 541 TCGv_i64 fpscr; 546 fpscr = place_from_fpscr(a->rt, UINT64_MAX); 553 TCGv_i64 t1, fpscr; 563 store_fpscr_masked(fpscr, FP_RN, t1, 0x0001); 569 TCGv_i64 t1, fpscr; 585 TCGv_i64 t1, fpscr; [all …]
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/qemu/linux-user/ppc/ |
H A D | signal.c | 302 __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]); in save_user_regs() 405 uint64_t fpscr; in restore_user_regs() local 410 __get_user(fpscr, &frame->mc_fregs[32]); in restore_user_regs() 411 env->fpscr = (uint32_t) fpscr; in restore_user_regs() 452 env->fpscr = 0; in setup_frame() 525 env->fpscr = 0; in setup_rt_frame()
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/qemu/bsd-user/arm/ |
H A D | signal.c | 145 uint32_t fpscr, mask; in set_mcontext() local 201 __get_user(fpscr, &vfp->mcv_fpscr); in set_mcontext() 202 vfp_set_fpscr(env, fpscr); in set_mcontext()
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/qemu/linux-user/arm/ |
H A D | signal.c | 63 abi_ulong fpscr; member 263 __put_user(vfp_get_fpscr(env), &vfpframe->ufp.fpscr); in setup_sigframe_vfp() 412 uint32_t fpscr, fpexc; in restore_sigframe_vfp() local 424 __get_user(fpscr, &vfpframe->ufp.fpscr); in restore_sigframe_vfp() 425 vfp_set_fpscr(env, fpscr); in restore_sigframe_vfp()
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/qemu/target/arm/ |
H A D | vfp_helper.c | 172 uint32_t i, fpscr; in HELPER() local 174 fpscr = env->vfp.xregs[ARM_VFP_FPSCR] in HELPER() 182 fpscr |= env->v7m.ltpsize << 16; in HELPER() 184 fpscr |= vfp_get_fpscr_from_host(env); in HELPER() 187 fpscr |= i ? FPCR_QC : 0; in HELPER() 189 return fpscr; in HELPER()
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H A D | arch_dump.c | 307 uint32_t fpscr; member 352 note.vfp.fpscr = cpu_to_dump32(s, vfp_get_fpscr(env)); in arm_write_elf32_vfp()
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/qemu/linux-user/sh4/ |
H A D | signal.c | 140 __put_user(regs->fpscr, &sc->sc_fpscr); in setup_sigcontext() 168 __get_user(regs->fpscr, &sc->sc_fpscr); in restore_sigcontext()
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/qemu/hw/ppc/ |
H A D | spapr_nested.c | 214 save->fpscr = env->fpscr; in nested_save_state() 313 ppc_store_fpscr(env, load->fpscr); in nested_load_state() 1002 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FPSCR, fpscr),
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/qemu/include/hw/ppc/ |
H A D | spapr_nested.h | 486 uint64_t fpscr; member
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