/qemu/tests/tcg/xtensa/ |
H A D | test_shift.S | 7 \prefix\()_ver \dst, \v, \imm 37 .macro slli_ver dst, v, imm 55 .if (\imm) 88 movi a2, \imm 95 movi a2, 32 - \imm 116 movi a2, \imm 123 movi a2, \imm 146 movi a2, \imm 153 movi a2, \imm 176 movi a2, \imm [all …]
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H A D | test_sar.S | 5 .macro test_sar prefix, imm 6 \prefix\()_set \imm 7 \prefix\()_ver \imm 22 .macro sar_set imm 23 movi a2, \imm 27 .macro sar_ver imm 37 .macro ssr_set imm 38 movi a2, \imm 42 .macro ssr_ver imm 52 .macro ssl_set imm [all …]
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/qemu/target/rx/ |
H A D | insns.decode | 25 &ri rd imm 27 &rri rd imm rs2 29 &mi rs ld mi imm 91 # ADC #imm, rd 113 # AND #imm, rd 125 # BCLR #imm, rs 222 # DIV #imm, rd 431 # MVTIPL #imm 448 # OR #imm, rd 476 # RACW #imm [all …]
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H A D | disas.c | 188 if (imm < 0x100) { in prt_ir() 414 prt_ir(ctx, "stz", a->imm, a->rd); in trans_STZ() 428 prt("rtsd\t#%d", a->imm << 2); in trans_RTSD_i() 443 prt_ir(ctx, "and", a->imm, a->rd); in trans_AND_ir() 466 prt_ir(ctx, "or", a->imm, a->rd); in trans_OR_ir() 488 prt_ir(ctx, "xor", a->imm, a->rd); in trans_XOR_ir() 503 prt_ir(ctx, "tst", a->imm, a->rd); in trans_TST_ir() 542 prt_ir(ctx, "adc", a->imm, a->rd); in trans_ADC_ir() 1079 prt("racw\t#%d", a->imm + 1); in trans_RACW() 1350 prt("movtipl\t#%d", a->imm); in trans_MVTIPL() [all …]
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H A D | translate.c | 461 TCGv imm, mem; in trans_MOV_im() local 462 imm = tcg_constant_i32(a->imm); in trans_MOV_im() 465 rx_gen_st(a->sz, imm, mem); in trans_MOV_im() 731 _imm = tcg_constant_i32(imm); in stcond() 1189 TCGv imm = tcg_constant_i32(a->imm); in trans_EMUL_ir() local 1216 TCGv imm = tcg_constant_i32(a->imm); in trans_EMULU_ir() local 1287 if (a->imm) { in trans_SHLL_irr() 1343 if (imm) { in shiftr_imm() 1800 TCGv imm = tcg_constant_i32(a->imm + 1); in trans_RACW() local 2115 TCGv imm; in trans_MVTC_i() local [all …]
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/qemu/target/riscv/ |
H A D | insn16.decode | 57 &i imm rs1 rd !extern 58 &s imm rs1 rs2 !extern 59 &j imm rd !extern 60 &b imm rs2 rs1 !extern 61 &u imm rd !extern 79 @cj ... ........... .. &j imm=%imm_cj 82 @c_lqsp ... . ..... ..... .. &i imm=%uimm_6bit_lq rs1=2 %rd 88 @c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd 89 @c_lui ... . ..... ..... .. &u imm=%imm_lui %rd 90 @c_jalr ... . ..... ..... .. &i imm=0 rs1=%rd [all …]
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H A D | translate.c | 564 if ((imm & 0x3) != 0) { in gen_jal() 585 tcg_gen_addi_tl(addr, src1, imm); in get_address() 781 imm = imm ? imm : 64; in ex_rvc_shiftli() 783 return imm; in ex_rvc_shiftli() 793 imm = imm | (imm & 32) << 1; in ex_rvc_shiftri() 794 imm = imm ? imm : 64; in ex_rvc_shiftri() 796 return imm; in ex_rvc_shiftri() 808 func(dest, src1, a->imm); in gen_logic_imm_fn() 814 func(desth, src1h, -(a->imm < 0)); in gen_logic_imm_fn() 854 func(dest, src1, a->imm); in gen_arith_imm_fn() [all …]
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/qemu/target/avr/ |
H A D | disas.c | 137 INSN(SUBI, "r%d, %d", a->rd, a->imm) 139 INSN(SBCI, "r%d, %d", a->rd, a->imm) 142 INSN(ANDI, "r%d, %d", a->rd, a->imm) 144 INSN(ORI, "r%d, %d", a->rd, a->imm) 156 INSN(DES, "%d", a->imm) 161 INSN(RJMP, ".%+d", a->imm * 2) 164 INSN(JMP, "0x%x", a->imm * 2) 165 INSN(RCALL, ".%+d", a->imm * 2) 168 INSN(CALL, "0x%x", a->imm * 2) 174 INSN(CPI, "r%d, %d", a->rd, a->imm) [all …]
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H A D | insn.decode | 43 &rd_imm rd imm 46 @op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6 47 @op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8 76 DES 1001 0100 imm:4 1011 88 @op_bit_imm .... .. imm:s7 bit:3 90 RJMP 1100 imm:s12 93 JMP 1001 010 ..... 110 . imm=%imm_call 94 RCALL 1101 imm:s12 97 CALL 1001 010 ..... 111 . imm=%imm_call 119 @ldst_d .. . . .. . rd:5 . ... &rd_imm imm=%ldst_d_imm [all …]
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/qemu/target/arm/tcg/ |
H A D | t16.decode | 25 &s_rri_rot !extern s rn rd imm rot 29 &ri !extern rd imm 31 &i !extern imm 33 &ldst_ri !extern p w u rn rt imm 37 &ci !extern cond imm 88 @ldst_ri_1 ..... imm:5 rn:3 rt:3 \ 91 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4 102 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2 111 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4 151 @addsub_2i ....... imm:3 rn:3 rd:3 \ [all …]
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H A D | t32.decode | 25 &s_rri_rot !extern s rn rd imm rot 31 &ri !extern rd imm 33 &i !extern imm 39 &ldst_ri !extern p w u rn rt imm 42 &ldrex !extern rn rt rt2 imm 148 &pkh imm=%imm5_12_6 237 &sat imm=%imm5_12_6 239 &sat sh=0 imm=0 359 &ci cond imm 573 &strex imm=0 [all …]
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H A D | a32.decode | 28 &s_rri_rot s rn rd imm rot 34 &ri rd imm 36 &i imm 42 &ldst_ri p w u rn rt imm 44 &strex rn rd rt rt2 imm 45 &ldrex rn rt rt2 imm 48 &sat rd rn satimm imm sh 49 &pkh rd rn rm imm tb 185 &msr_i r mask rot imm 378 &strex imm=0 rt2=15 [all …]
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H A D | a64.decode | 29 &ri rd imm 30 &rri_sf rd rn imm sf 31 &i imm 126 &movw rd sf imm hw 152 &extract rd rn rm imm sf 166 &cbz rt imm sf nz 172 &tbz rt imm nz bitpos 309 &ldlit rt imm sz sign 521 &ldapr_stlr_i rn rt imm sz sign ext 586 &ldst_tag rn rt imm p w [all …]
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H A D | vfp.decode | 83 VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp 95 VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \ 97 VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \ 100 VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \ 102 VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \ 158 vd=%vd_sp imm=%vmov_imm 160 vd=%vd_sp imm=%vmov_imm 162 vd=%vd_dp imm=%vmov_imm 235 vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op 237 vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op [all …]
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/qemu/tests/qemu-iotests/ |
H A D | 026.out.nocache | 6 Event: l1_update; errno: 5; imm: off; once: on; write 11 Event: l1_update; errno: 5; imm: off; once: on; write -b 16 Event: l1_update; errno: 5; imm: off; once: off; write 23 Event: l1_update; errno: 5; imm: off; once: off; write -b 30 Event: l1_update; errno: 28; imm: off; once: on; write 40 Event: l1_update; errno: 28; imm: off; once: off; write 54 Event: l2_load; errno: 5; imm: off; once: on; write 62 Event: l2_load; errno: 5; imm: off; once: on; write -b 70 Event: l2_load; errno: 5; imm: off; once: off; write 86 Event: l2_load; errno: 28; imm: off; once: on; write [all …]
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H A D | 026.out | 6 Event: l1_update; errno: 5; imm: off; once: on; write 11 Event: l1_update; errno: 5; imm: off; once: on; write -b 16 Event: l1_update; errno: 5; imm: off; once: off; write 23 Event: l1_update; errno: 5; imm: off; once: off; write -b 30 Event: l1_update; errno: 28; imm: off; once: on; write 40 Event: l1_update; errno: 28; imm: off; once: off; write 54 Event: l2_load; errno: 5; imm: off; once: on; write 62 Event: l2_load; errno: 5; imm: off; once: on; write -b 70 Event: l2_load; errno: 5; imm: off; once: off; write 86 Event: l2_load; errno: 28; imm: off; once: on; write [all …]
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H A D | 026 | 84 for imm in off; do 92 immediately = "$imm" 99 echo "Event: $event; errno: $errno; imm: $imm; once: $once; write $vmstate" 142 for imm in off; do 150 immediately = "$imm" 157 echo "Event: $event; errno: $errno; imm: $imm; once: $once; write $vmstate" 182 for imm in off; do 189 immediately = "$imm" 196 echo "Event: $event; errno: $errno; imm: $imm; once: $once"
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/qemu/hw/mips/ |
H A D | bootloader.c | 112 insn = deposit32(insn, 0, 16, imm); in bl_gen_i_type() 162 bl_gen_i_type(p, 0x0f, 0, rt, imm); in bl_gen_lui() 180 bl_gen_i_type(p, 0x0d, rs, rt, imm); in bl_gen_ori() 219 bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); in bl_gen_li() 222 bl_gen_lui(p, rt, extract32(imm, 16, 16)); in bl_gen_li() 223 bl_gen_ori(p, rt, rt, extract32(imm, 0, 16)); in bl_gen_li() 229 bl_gen_li(p, rt, extract64(imm, 32, 32)); in bl_gen_dli() 231 bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); in bl_gen_dli() 233 bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); in bl_gen_dli() 239 bl_gen_dli(p, rt, imm); /* 64bit */ in bl_gen_load_ulong() [all …]
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/qemu/target/microblaze/ |
H A D | insns.decode | 24 &typeb rd ra imm 25 &typeb_br rd imm 26 &typeb_bc ra imm 27 &type_msr rd imm 45 @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb 54 # them back together as "imm". Doing this makes it easiest to 59 @type_msr ...... rd:5 ...... imm:15 &type_msr 162 get 011011 rd:5 00000 0 ctrl:5 000000 imm:4 168 imm 101100 00000 00000 imm:16 186 mbar 101110 imm:5 00010 0000 0000 0000 0100 [all …]
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H A D | translate.c | 259 imm = tcg_constant_i32(arg->imm); in do_typeb_val() 261 fn(rd, ra, imm); in do_typeb_val() 1164 uint32_t imm = arg->imm; in trans_brki() local 1166 if (trap_userspace(dc, imm != 0x8 && imm != 0x18)) { in trans_brki() 1180 switch (imm) { in trans_brki() 1193 if (imm != 0x18) { in trans_brki() 1196 if (imm == 0x8 || imm == 0x18) { in trans_brki() 1309 uint32_t imm = arg->imm; in do_msrclrset() local 1323 if (imm & MSR_C) { in do_msrclrset() 1333 if (imm != 0) { in do_msrclrset() [all …]
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/qemu/target/hexagon/ |
H A D | gen_trans_funcs.py | 51 imm = immre.findall(hex_common.semdict[tag]) 52 if len(imm) == 0: 55 letter = re.split("\\(", imm[0])[1] 109 for imm in imms: 110 imm_type = imm[0] 113 imm_shift = int(imm[2]) if imm[2] else 0
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/qemu/target/loongarch/ |
H A D | insns.decode | 20 &i imm 21 &r_i rd imm 25 &rr_i rd rj imm 26 &hint_r_i hint rj imm 44 &fr_i fd rj imm 52 &i_rr imm rj rk 53 &cop_r_i cop rj imm 54 &j_i rj imm 510 &vv_i vd vj imm 513 &vr_i vd rj imm [all …]
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/qemu/target/loongarch/tcg/ |
H A D | vec_helper.c | 1281 if (imm == 0) { in HELPER() 1332 if (imm == 0) { in HELPER() 1568 if (imm == 0) { 1634 if (imm == 0) { in do_vssrani_d_q() 1746 if (imm == 0) { in do_vssrani_du_q() 1998 if (imm == 0) { 2066 if (imm == 0) { in do_vssrarni_d_q() 2178 if (imm == 0) { in do_vssrarni_du_q() 3410 temp.D(2 * i) = (imm & 2 ? Vj : Vd)->D((imm & 1) + 2 * i); in HELPER() 3411 temp.D(2 * i + 1) = (imm & 8 ? Vj : Vd)->D(((imm >> 2) & 1) + 2 * i); in HELPER() [all …]
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/qemu/target/sparc/ |
H A D | insns.decode | 38 &r_r_ri rd rs1 rs2_or_imm imm:bool 40 @r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri 42 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool 240 POPC 10 rd:5 101110 00000 imm:1 rs2_or_imm:s13 \ 572 &r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool 581 &r_r_ri_asi imm=1 asi=-2 583 &r_r_ri_asi rd=%dfp_rd imm=0 585 &r_r_ri_asi rd=%dfp_rd imm=1 asi=-2 587 &r_r_ri_asi rd=%qfp_rd imm=0 589 &r_r_ri_asi rd=%qfp_rd imm=1 asi=-2 [all …]
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/qemu/target/mips/tcg/ |
H A D | mips16e_translate.c.inc | 460 int16_t imm, offset; 481 gen_addiupc(ctx, rx, imm, 0, 1); 524 imm = ctx->opcode & 0xf; 525 imm = imm | ((ctx->opcode >> 20) & 0x7f) << 4; 526 imm = imm | ((ctx->opcode >> 16) & 0xf) << 11; 527 imm = (int16_t) (imm << 1) >> 1; 543 gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm); 557 gen_st(ctx, OPC_SW, 31, 29, imm); 757 int16_t imm = (int8_t) ctx->opcode; 764 int16_t imm = (uint8_t) ctx->opcode; [all …]
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