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Searched refs:imm5 (Results 1 – 3 of 3) sorted by relevance

/qemu/target/riscv/
H A Dxthead.decode20 %imm5 20:s5
32 &th_meminc rd rs1 imm5 imm2
44 @th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 %imm5 %imm2
/qemu/target/riscv/insn_trans/
H A Dtrans_xthead.c.inc555 * Load with memop from indexed address and add (imm5 << imm2) to rs1.
557 * If preinc, then the load address is rs1 + (imm5) << imm2).
566 int imm = a->imm5 << a->imm2;
579 * Store with memop to indexed address and add (imm5 << imm2) to rs1.
581 * If preinc, then the store address is rs1 + (imm5) << imm2).
586 int imm = a->imm5 << a->imm2;
/qemu/target/arm/tcg/
H A Dtranslate-a64.c7782 int imm5 = extract32(insn, 5, 5); in disas_fp_imm() local
7789 if (mos || imm5) { in disas_fp_imm()