/qemu/target/arm/tcg/ |
H A D | sve.decode | 197 # Predicate output, vector and immediate input, 202 # Basic Load/Store with 9-bit immediate offset 340 # SVE bitwise shift by immediate (predicated) 440 # SVE index generation (immediate start, immediate increment) 466 # SVE bitwise shift by immediate (unpredicated) 525 # SVE broadcast bitmask immediate 533 # SVE copy integer immediate (predicated) 693 # SVE integer compare with unsigned immediate 701 # SVE integer compare with signed immediate 835 # SVE integer min/max immediate (unpredicated) [all …]
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H A D | t16.decode | 84 # Load/store word/byte (immediate offset) 98 # Load/store halfword (immediate offset) 120 # Add PC/SP (immediate) 133 # Shift (immediate) 149 # Add/subtract (two low registers and immediate) 157 # Add, subtract, compare, move (one low register and immediate) 178 # Adjust SP (immediate)
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H A D | t32.decode | 166 # Data-processing (immediate) 207 # Data processing (plain binary immediate) 425 # Load/store (register, immediate, literal) 465 PLD 1111 1000 1001 ---- 1111 ------------ # (immediate T1) 470 PLD 1111 1000 0001 ---- 1111 1100 -------- # (immediate T2) 485 PLDW 1111 1000 1011 ---- 1111 ------------ # (immediate T1) 490 PLDW 1111 1000 0011 ---- 1111 1100 -------- # (immediate T2) 513 PLI 1111 1001 1001 ---- 1111 ------------ # (immediate T1) 518 PLI 1111 1001 0001 ---- 1111 1100 -------- # (immediate T2) 735 # LE and WLS immediate
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H A D | a64.decode | 85 # Add/subtract (immediate) 101 # Add/subtract (immediate with tags) 109 # Logical (immediate) 124 # Move wide (immediate) 250 # These are architecturally all "MSR (immediate)"; we decode the destination 383 # Load/store register (unscaled immediate) 452 # Load/store with an unsigned 12 bit immediate, which is scaled by the 453 # element size. The function gets the sz:imm and returns the scaled immediate. 516 # LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous
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H A D | a32.decode | 111 # Data-processing (immediate) 183 # MSR (immediate) and hints 308 # Load/Store Dual, Half, Signed Byte (immediate) 344 # Load/Store word and unsigned byte (immediate)
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H A D | mve.decode | 37 # 1imm format immediate 399 # VIDUP, VDDUP format immediate: 1 << (immh:imml) 587 # Logical immediate operations (1 reg and modified-immediate) 599 # Shifts by immediate
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H A D | vfp.decode | 229 # VCVT between floating-point and fixed-point. The immediate value
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H A D | neon-dp.decode | 365 # 1-reg-and-modified-immediate grouping:
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/qemu/target/mips/tcg/ |
H A D | octeon.decode | 27 # SEQI rt, rs, immediate 29 # SNEI rt, rs, immediate
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/qemu/target/i386/tcg/ |
H A D | emit.c.inc | 451 uint8_t b = decode->immediate; 1093 if (decode->immediate == 0) { 2614 if (decode->immediate >= 16) { 2627 if (decode->immediate >= 16) { 2640 if (decode->immediate >= 16) { 2641 decode->immediate = 15; 2652 if (decode->immediate >= 32) { 2665 if (decode->immediate >= 32) { 2679 decode->immediate = 31; 3738 int val = decode->immediate; [all …]
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H A D | decode-new.h | 301 target_ulong immediate; member
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/qemu/target/avr/ |
H A D | insn.decode | 82 # The 22-bit immediate is partially in the opcode word, 121 # The 16-bit immediate is completely in the next word. 124 # Defer reading the immediate until trans_{LDS,STS}.
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/qemu/tcg/aarch64/ |
H A D | tcg-target.c.inc | 228 /* Return true if v32 is a valid float32 immediate. */ 390 /* Compare and branch (immediate). */ 394 /* Conditional branch (immediate). */ 397 /* Test and branch (immediate). */ 401 /* Unconditional branch (immediate). */ 457 /* Add/subtract immediate instructions. */ 471 /* Logical immediate instructions. */ 477 /* Move wide immediate instructions. */ 544 /* AdvSIMD modified immediate */ 550 /* AdvSIMD scalar shift by immediate */ [all …]
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/qemu/target/hexagon/imported/ |
H A D | alu.idef | 43 COND_ALU(A2_paddi,"Rd32=add(Rs32,#s8)","Conditionally Add Register and immediate",fIMMEXT(siV); RdV… 66 "Add a signed immediate to a register", 71 "Add immediate to PC", 247 "This instruction carries the 26 most-significant immediate bits for the next instruction", 255 "transfer signed immediate to register",{ fIMMEXT(siV); RdV=siV;}) 273 "Combine a word and an immediate into a register pair", 279 "Combine a word and an immediate into a register pair", 435 "Subtract register from immediate",{ fIMMEXT(siV); RdV=siV-RsV;}) 438 "logical AND with immediate",{ fIMMEXT(siV); RdV=RsV&siV;}) 441 "logical OR with immediate",{ fIMMEXT(siV); RdV=RsV|siV;})
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H A D | compare.idef | 104 /* Scalar compare instructions W/ immediate */ 277 "Scalar MUX register immediate", 282 "Scalar MUX register immediate",
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H A D | float.idef | 131 /* More immediate bits should probably be used for more precision? */ 294 /* More immediate bits should probably be used for more precision? */
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H A D | mpy.idef | 75 "32-bit Multiply by unsigned immediate", 79 "32-bit Multiply by unsigned immediate, negate result", 83 "32-bit Multiply-Add by unsigned immediate", 87 "32-bit Multiply-Subtract by unsigned immediate",
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H A D | ldst.idef | 322 /* The set of 32-bit store immediate instructions */ 332 /* The set of 32-bit store immediate instructions */
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H A D | shift.idef | 169 Q6INSN(S4_lsli,"Rd32=lsl(#s6,Rt32)",ATTRIBS(), "Shift an immediate left by register amount", 367 ATTRIBS(), "Form mask from immediate",
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/qemu/docs/devel/ |
H A D | conflict-resolution.rst | 26 if the problem requires immediate escalation, report the issue to the QEMU
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/qemu/target/hexagon/idef-parser/ |
H A D | README.rst | 58 - Fill in the output function signature with the immediate integers 169 value in case of an immediate constant, and decorates the token with the 236 immediate value 1234 253 ``riV``, etc. refer to immediate arguments and will map to C integers. 400 iterate on immediate values, therefore their iteration ranges are always known
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/qemu/target/microblaze/ |
H A D | insns.decode | 44 # Officially typeb, but any immediate extension is unused.
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/qemu/tcg/arm/ |
H A D | tcg-target.c.inc | 216 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 235 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 413 /* Return true if v16 is a valid 16-bit shifted immediate. */ 428 /* Return true if v32 is a valid 32-bit shifted immediate. */ 451 /* Return true if v32 is a valid 32-bit shifting ones immediate. */ 486 /* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 605 not wish to include an immediate shift at this point. */ 1492 * isn't worth checking for an immediate operand for BIC. 1771 * shifted immediate from pc.
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/qemu/tcg/s390x/ |
H A D | tcg-target.c.inc | 893 /* load a register with an immediate value */ 968 the high 44 bits must come from an immediate load. */ 1624 * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. 1625 * If the immediate we've been given does not fit that range, we'll 2115 /* ??? LLC (RXY format) is only present with the extended-immediate 2126 /* ??? LLH (RXY format) is only present with the extended-immediate 3450 which = "extended-immediate";
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/qemu/tcg/sparc64/ |
H A D | tcg-target.c.inc | 716 Note that the immediate range is one bit smaller, so we must check 1361 /* Limit immediate shift count lest we create an illegal insn. */ 1451 /* Limit immediate shift count lest we create an illegal insn. */
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