/qemu/hw/m68k/ |
H A D | mcf_intc.c | 28 uint64_t imr; member 43 active = (s->ipr | s->ifr) & s->enabled & ~s->imr; in mcf_intc_update() 74 return (uint32_t)(s->imr >> 32); in mcf_intc_read() 76 return (uint32_t)s->imr; in mcf_intc_read() 115 s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32); in mcf_intc_write() 118 s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val; in mcf_intc_write() 122 s->imr = ~0ull; in mcf_intc_write() 124 s->imr |= (0x1ull << (val & 0x3f)); in mcf_intc_write() 129 s->imr = 0ull; in mcf_intc_write() 131 s->imr &= ~(0x1ull << (val & 0x3f)); in mcf_intc_write() [all …]
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H A D | mcf5206.c | 170 uint16_t imr; /* 1 == interrupt is masked. */ member 192 active = s->ipr & ~s->imr; in m5206_find_pending_irq() 282 s->imr = 0x3ffe; in m5206_mbar_reset() 303 case 0x36: return s->imr; in m5206_mbar_read() 353 s->imr = value; in m5206_mbar_write()
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/qemu/hw/gpio/ |
H A D | mpc8xxx.c | 43 uint32_t imr; member 56 VMSTATE_UINT32(imr, MPC8XXXGPIOState), 64 qemu_set_irq(s->irq, !!(s->ier & s->imr)); in mpc8xxx_gpio_update() 87 return s->imr; in mpc8xxx_gpio_read() 140 s->imr = value; in mpc8xxx_gpio_write() 158 s->imr = 0; in mpc8xxx_gpio_reset()
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H A D | imx_gpio.c | 72 qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0); in imx_gpio_update_int() 73 qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0); in imx_gpio_update_int() 75 qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0); in imx_gpio_update_int() 180 reg_value = s->imr; in imx_gpio_read() 239 s->imr = value; in imx_gpio_write() 285 VMSTATE_UINT32(imr, IMXGPIOState), 308 s->imr = 0; in imx_gpio_reset()
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H A D | zaurus.c | 48 uint16_t imr; member 97 return s->imr; in scoop_read() 140 s->imr = value; in scoop_write() 239 VMSTATE_UINT16(imr, ScoopInfo),
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/qemu/hw/misc/ |
H A D | stm32l4x5_exti.c | 85 s->imr[bank] = exti_romask[bank]; in stm32l4x5_exti_reset_hold() 106 if (!extract32(s->imr[bank], irq, 1)) { in stm32l4x5_exti_set_irq() 138 r = s->imr[bank]; in stm32l4x5_exti_read() 184 s->imr[bank] = val64 & valid_mask(bank); in stm32l4x5_exti_write() 201 const uint32_t pend = set & ~s->swier[bank] & s->imr[bank] & in stm32l4x5_exti_write() 261 VMSTATE_UINT32_ARRAY(imr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
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H A D | lasi.c | 68 val = s->imr; in lasi_chip_read_with_attrs() 130 s->imr = val; in lasi_chip_write_with_attrs() 214 VMSTATE_UINT32(imr, LasiState), 233 if (bit & s->imr) { in lasi_set_irq()
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/qemu/hw/net/ |
H A D | mv88w8618_eth.c | 101 uint32_t imr; member 156 if (s->icr & s->imr) { in eth_receive() 242 return s->imr; in mv88w8618_eth_read() 279 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) { in mv88w8618_eth_write() 289 s->imr = value; in mv88w8618_eth_write() 290 if (s->icr & s->imr) { in mv88w8618_eth_write() 364 VMSTATE_UINT32(imr, mv88w8618_eth_state),
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H A D | ne2000.c | 143 isr = (s->isr & s->imr) & 0x7f; in ne2000_update_irq() 146 isr ? 1 : 0, s->isr, s->imr); in ne2000_update_irq() 315 s->imr = val; in ne2000_ioport_write() 623 VMSTATE_UINT8(imr, NE2000State),
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H A D | ne2000.h | 27 uint8_t imr; member
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/qemu/target/openrisc/ |
H A D | mmu.c | 41 uint32_t imr = cpu->env.tlb.itlb[idx].mr; in get_phys_mmu() local 54 imr = itr = 0; in get_phys_mmu() 59 match = (imr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_EXEC; in get_phys_mmu() 63 valid = imr & 1 ? PAGE_EXEC : 0; in get_phys_mmu()
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/qemu/hw/i386/kvm/ |
H A D | i8259.c | 54 s->imr = kpic->imr; in kvm_pic_get() 82 kpic->imr = s->imr; in kvm_pic_put()
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/qemu/hw/pci-host/ |
H A D | dino.c | 141 val = s->imr; in dino_chip_read_with_attrs() 155 val = s->ilr & s->imr & ~s->icr; in dino_chip_read_with_attrs() 158 val = s->ilr & s->imr & s->icr; in dino_chip_read_with_attrs() 238 s->imr = val; in dino_chip_write_with_attrs() 293 VMSTATE_UINT32(imr, DinoState), 387 if (ena & s->imr) { in dino_set_irq()
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/qemu/hw/char/ |
H A D | ipoctal232.c | 113 uint8_t imr; member 150 VMSTATE_UINT8(imr, SCC2698Block), 186 if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) { in update_irq() 338 uint8_t old_imr = blk->imr; in io_write() 380 blk->imr = reg; in io_write() 392 if (old_isr != blk->isr || old_imr != blk->imr) { in io_write()
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H A D | mcf_uart.c | 27 uint8_t imr; member 78 qemu_set_irq(s->irq, (s->isr & s->imr) != 0); in OBJECT_DECLARE_SIMPLE_TYPE() 225 s->imr = val; in mcf_uart_write() 244 s->imr = 0; in mcf_uart_reset()
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/qemu/hw/intc/ |
H A D | i8259.c | 82 mask = s->irr & ~s->imr; in pic_get_irq() 92 mask &= ~s->imr; in pic_get_irq() 113 trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); in pic_update_irq() 301 s->imr = val; in pic_ioport_write() 347 ret = s->imr; in pic_ioport_read()
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H A D | i8259_common.c | 41 s->imr = 0; in pic_reset_common() 142 s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add, in pic_print_info() 174 VMSTATE_UINT8(imr, PICCommonState),
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/qemu/net/ |
H A D | dgram.c | 148 struct ip_mreq imr; in net_dgram_mcast_create() local 192 imr.imr_multiaddr = mcastaddr->sin_addr; in net_dgram_mcast_create() 194 imr.imr_interface = *localaddr; in net_dgram_mcast_create() 196 imr.imr_interface.s_addr = htonl(INADDR_ANY); in net_dgram_mcast_create() 200 &imr, sizeof(struct ip_mreq)); in net_dgram_mcast_create() 204 inet_ntoa(imr.imr_multiaddr)); in net_dgram_mcast_create()
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H A D | socket.c | 217 struct ip_mreq imr; in net_socket_mcast_create() local 261 imr.imr_multiaddr = mcastaddr->sin_addr; in net_socket_mcast_create() 263 imr.imr_interface = *localaddr; in net_socket_mcast_create() 265 imr.imr_interface.s_addr = htonl(INADDR_ANY); in net_socket_mcast_create() 269 &imr, sizeof(struct ip_mreq)); in net_socket_mcast_create() 273 inet_ntoa(imr.imr_multiaddr)); in net_socket_mcast_create()
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/qemu/hw/arm/ |
H A D | musicpal.c | 833 uint32_t imr; member 895 ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { in musicpal_gpio_pin_event() 926 return s->imr & 0xFFFF; in musicpal_gpio_read() 928 return s->imr >> 16; in musicpal_gpio_read() 971 s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); in musicpal_gpio_write() 974 s->imr = (s->imr & 0xFFFF) | (value << 16); in musicpal_gpio_write() 993 s->imr = 0; in musicpal_gpio_reset() 1023 VMSTATE_UINT32(imr, musicpal_gpio_state),
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/qemu/hw/display/ |
H A D | tc6393xb.c | 126 uint8_t imr; member 317 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr)); in tc6393xb_nand_irq() 364 return s->nand.imr; in tc6393xb_nand_readb() 405 s->nand.imr = value; in tc6393xb_nand_writeb()
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/qemu/include/hw/misc/ |
H A D | stm32l4x5_exti.h | 41 uint32_t imr[EXTI_NUM_REGISTER]; member
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H A D | lasi.h | 67 uint32_t imr; member
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/qemu/include/hw/gpio/ |
H A D | imx_gpio.h | 54 uint32_t imr; member
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/qemu/include/hw/isa/ |
H A D | i8259_internal.h | 49 uint8_t imr; /* interrupt mask register */ member
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