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Searched refs:inc (Results 1 – 25 of 73) sorted by relevance

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/qemu/target/hexagon/
H A Dmeson.build44 # tcg_func_table_generated.c.inc
45 # printinsn_generated.h.inc
46 # op_attribs_generated.h.inc
47 # opcodes_def_generated.h.inc
50 'tcg_func_table_generated.c.inc',
59 'printinsn_generated.h.inc',
68 'op_attribs_generated.h.inc',
77 'opcodes_def_generated.h.inc',
183 'decode_hvx_generated.c.inc',
362 # tcg_funcs_generated.c.inc
[all …]
H A DREADME45 gen_opcodes_def.py -> opcodes_def_generated.h.inc
46 gen_printinsn.py -> printinsn_generated.h.inc
47 gen_op_attribs.py -> op_attribs_generated.h.inc
48 gen_helper_protos.py -> helper_protos_generated.h.inc
49 gen_tcg_funcs.py -> tcg_funcs_generated.c.inc
51 gen_helper_funcs.py -> helper_funcs_generated.c.inc
73 helper_protos_generated.h.inc
76 tcg_funcs_generated.c.inc
91 helper_funcs_generated.c.inc
199 <BUILD_DIR>/target/hexagon/decode_*_generated.c.inc
[all …]
/qemu/docs/system/
H A Dqemu-manpage.rst5 should simply include the .rst.inc files corresponding to the
25 .. include:: target-i386-desc.rst.inc
41 .. include:: keys.rst.inc
43 .. include:: mux-chardev.rst.inc
49 .. include:: device-url-syntax.rst.inc
H A Dqemu-cpu-models.rst17 .. include:: cpu-models-x86.rst.inc
18 .. include:: cpu-models-mips.rst.inc
H A Dkeys.rst6 .. include:: keys.rst.inc
H A Dmux-chardev.rst6 .. include:: mux-chardev.rst.inc
H A Dqemu-block-drivers.rst17 .. include:: qemu-block-drivers.rst.inc
H A Dinvocation.rst23 .. include:: device-url-syntax.rst.inc
/qemu/hw/timer/
H A Da9gtimer.c93 if (gtb->control & R_CONTROL_AUTO_INCREMENT && gtb->inc) { in a9_gtimer_update()
94 uint64_t inc = in a9_gtimer_update() local
95 QEMU_ALIGN_UP(update.new - gtb->compare, gtb->inc); in a9_gtimer_update()
97 PRId64 "\n", inc); in a9_gtimer_update()
98 gtb->compare += inc; in a9_gtimer_update()
164 ret = gtb->inc; in a9_gtimer_read()
218 gtb->inc = value; in a9_gtimer_write()
288 gtb->inc = 0; in a9_gtimer_reset()
335 VMSTATE_UINT32(inc, A9GTimerPerCPU),
/qemu/docs/devel/
H A Dci.rst12 .. include:: ci-definitions.rst.inc
13 .. include:: ci-jobs.rst.inc
14 .. include:: ci-runners.rst.inc
/qemu/scripts/
H A Dgit.orderfile17 *.rst.inc
34 *.h.inc
41 *.c.inc
H A Dextract-vsssdk-headers17 if test -e inc; then
33 mv "$tmpdir/Program Files/Microsoft/VSSSDK72/inc" inc
H A Dupdate-mips-syscall-args.sh13 INC=linux-user/mips/syscall-args-o32.c.inc
/qemu/tests/tcg/cris/bare/
H A Dcheck_addcv17.s5 .macro addc Rs Rd inc=0
7 .word (\Rd << 12) | \Rs | (\inc << 10) | 0x09a0
55 addc 4 3 inc=1
/qemu/tests/tcg/hexagon/
H A Dcirc.c98 static int32_t build_mreg(int32_t inc, int32_t K, int32_t len) in INIT()
100 return ((inc & 0x780) << 21) | in INIT()
102 ((inc & 0x7f) << 17) | in INIT()
221 void __check_load(int line, int32_t i, int64_t res, int32_t inc, int32_t size) in __check_load() argument
223 int32_t expect = (i * inc); in __check_load()
295 TYPE circ_val_##SZ(int i, int32_t inc, int32_t size) \ in TEST_LOAD_REG()
298 int elem = i * inc; \ in TEST_LOAD_REG()
322 void check_store_##SZ(int32_t inc, int32_t size) \
326 i, BUF[i], circ_val_##SZ(i, inc, size)); \
327 check64(BUF[i], circ_val_##SZ(i, inc, size)); \
/qemu/hw/intc/
H A Dppc-uic.c55 int start, end, inc, i; in ppcuic_trigger_irq() local
80 inc = -1; in ppcuic_trigger_irq()
84 inc = 1; in ppcuic_trigger_irq()
87 for (i = start; i <= end; i += inc) { in ppcuic_trigger_irq()
89 uic->uicvr += (i - start) * 512 * inc; in ppcuic_trigger_irq()
/qemu/
H A D.gitattributes1 *.c.inc diff=c
2 *.h.inc diff=c
H A D.editorconfig30 [*.{c,h,c.inc,h.inc}]
/qemu/hw/dma/
H A Dpl330.c188 bool inc; member
533 entry->inc = inc; in pl330_queue_put_insn()
731 bool inc; in pl330_dmald() local
748 inc = !!(ch->control & 1); in pl330_dmald()
909 bool inc; in pl330_dmast() local
922 inc = !!((ch->control >> 14) & 1); in pl330_dmast()
956 bool inc; in pl330_dmastz() local
960 inc = !!((ch->control >> 14) & 1); in pl330_dmastz()
963 if (inc) { in pl330_dmastz()
1194 if (q->inc) { in pl330_exec_cycle()
[all …]
/qemu/fpu/
H A Dsoftfloat-parts.c.inc153 uint64_t inc;
168 inc = frac_lsbm1;
172 inc = 0;
175 inc = p->sign ? 0 : round_mask;
179 inc = p->sign ? round_mask : 0;
200 if (frac_addi(p, p, inc)) {
287 frac_addi(p, p, inc);
990 inc = frac_lsbm1;
993 inc = 0;
1009 if (frac_addi(a, a, inc)) {
[all …]
/qemu/target/xtensa/
H A Dimport_core.sh26 sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c.inc
39 > "$TARGET"/xtensa-modules.c.inc
/qemu/docs/system/i386/
H A Dcpu.rst1 .. include:: ../cpu-models-x86.rst.inc
H A Dpc.rst7 .. include:: ../target-i386-desc.rst.inc
/qemu/tests/qtest/
H A Dnpcm7xx_watchdog_timer-test.c175 int inc = g_test_quick() ? 3 : 1; in test_prescaler() local
177 for (int wtclk = 0; wtclk < 4; wtclk += inc) { in test_prescaler()
178 for (int wtis = 0; wtis < 4; wtis += inc) { in test_prescaler()
/qemu/include/hw/timer/
H A Da9gtimer.h66 uint32_t inc; member

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