| /qemu/target/arm/tcg/ |
| H A D | cpu32.c | 982 { .name = "arm926", .initfn = arm926_initfn },
983 { .name = "arm946", .initfn = arm946_initfn },
984 { .name = "arm1026", .initfn = arm1026_initfn },
1001 { .name = "ti925t", .initfn = ti925t_initfn },
1002 { .name = "sa1100", .initfn = sa1100_initfn },
1003 { .name = "sa1110", .initfn = sa1110_initfn },
1004 { .name = "pxa250", .initfn = pxa250_initfn },
1005 { .name = "pxa255", .initfn = pxa255_initfn },
1006 { .name = "pxa260", .initfn = pxa260_initfn },
1007 { .name = "pxa261", .initfn = pxa261_initfn },
[all …]
|
| H A D | cpu-v7m.c | 267 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
269 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
271 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
273 { .name = "cortex-m7", .initfn = cortex_m7_initfn,
275 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
277 { .name = "cortex-m55", .initfn = cortex_m55_initfn,
|
| H A D | cpu64.c | 1299 { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
1300 { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
1301 { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
1302 { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
1303 { .name = "cortex-a710", .initfn = aarch64_a710_initfn },
1304 { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
1305 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
1306 { .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn },
1307 { .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn },
|
| /qemu/target/tricore/ |
| H A D | cpu.c | 202 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ argument
205 .instance_init = initfn, \
|
| /qemu/target/avr/ |
| H A D | cpu.c | 353 void (*initfn)(Object *obj); member
357 #define DEFINE_AVR_CPU_TYPE(model, initfn) \ argument
360 .instance_init = initfn, \
|
| /qemu/target/arm/ |
| H A D | cpu64.c | 751 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
752 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
753 { .name = "max", .initfn = aarch64_max_initfn },
755 { .name = "host", .initfn = aarch64_host_initfn },
816 acc->info->initfn(obj); in aarch64_cpu_instance_init()
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| H A D | cpu.c | 2717 acc->info->initfn(obj); in arm_cpu_instance_init()
|
| H A D | cpu.h | 1104 void (*initfn)(Object *obj); member
|
| /qemu/include/hw/i386/ |
| H A D | pc.h | 324 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ argument
329 mc->init = initfn; \
|
| /qemu/target/alpha/ |
| H A D | cpu.c | 255 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \ argument
258 .instance_init = initfn, \
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| /qemu/target/cris/ |
| H A D | cpu.c | 295 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ argument
298 .class_init = initfn, \
|
| /qemu/target/sh4/ |
| H A D | cpu.c | 294 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ argument
299 .instance_init = initfn, \
|
| /qemu/target/openrisc/ |
| H A D | cpu.c | 269 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ argument
272 .instance_init = initfn, \
|
| /qemu/target/hexagon/ |
| H A D | cpu.c | 358 #define DEFINE_CPU(type_name, initfn) \ argument
362 .instance_init = initfn \
|
| /qemu/target/riscv/ |
| H A D | cpu.c | 2471 #define DEFINE_CPU(type_name, misa_mxl_max, initfn) \ argument
2475 .instance_init = (initfn), \
2480 #define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ argument
2484 .instance_init = (initfn), \
2489 #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \ argument
2493 .instance_init = (initfn), \
2498 #define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \ argument
2502 .instance_init = (initfn), \
2507 #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \ argument
2511 .instance_init = (initfn), \
|
| /qemu/target/loongarch/ |
| H A D | cpu.c | 819 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ argument
822 .instance_init = initfn, \
|