| /qemu/contrib/plugins/ |
| H A D | hotblocks.c | 39 unsigned long insns; member
78 rec->insns, in plugin_exit()
113 size_t insns = qemu_plugin_tb_n_insns(tb); in vcpu_tb_trans() local
114 uint64_t hash = pc ^ insns; in vcpu_tb_trans()
124 cnt->insns = insns; in vcpu_tb_trans()
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| H A D | howvec.c | 38 static GHashTable *insns; variable
208 counts = g_hash_table_get_values(insns); in plugin_exit()
228 g_hash_table_destroy(insns); in plugin_exit()
241 insns = g_hash_table_new_full(NULL, g_direct_equal, NULL, &free_record); in plugin_init()
286 icount = (InsnExecCount *) g_hash_table_lookup(insns, in find_counter()
298 g_hash_table_insert(insns, GUINT_TO_POINTER(opcode), in find_counter()
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| H A D | lockstep.c | 47 uint64_t insns; member
161 prev->block->pc, prev->block->insns, in report_divergance()
217 insn_count += bi->insns; in vcpu_tb_exec()
230 bi->insns = qemu_plugin_tb_n_insns(tb); in vcpu_tb_trans()
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| /qemu/accel/tcg/ |
| H A D | plugin-gen.c | 296 insn = g_ptr_array_index(plugin_tb->insns, insn_idx); in plugin_gen_inject()
358 insn = g_ptr_array_index(plugin_tb->insns, insn_idx); in plugin_gen_inject()
403 ptb->insns = g_ptr_array_new(); in plugin_gen_tb_start()
419 if (n <= ptb->insns->len) { in plugin_gen_insn_start()
420 insn = g_ptr_array_index(ptb->insns, n - 1); in plugin_gen_insn_start()
422 assert(n - 1 == ptb->insns->len); in plugin_gen_insn_start()
424 g_ptr_array_add(ptb->insns, insn); in plugin_gen_insn_start()
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| /qemu/docs/devel/ |
| H A D | tcg-plugins.rst | 217 bb's: 2277338, insns: 158483046
239 cpu 0 insns: 46765
240 cpu 1 insns: 3694
241 cpu 2 insns: 3694
242 cpu 3 insns: 2994
243 cpu 4 insns: 1497
244 cpu 5 insns: 1497
245 cpu 6 insns: 1497
246 cpu 7 insns: 1497
247 total insns: 63135
[all …]
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| /qemu/target/rx/ |
| H A D | meson.build | 2 decodetree.process('insns.decode', extra_args: [ '--varinsnwidth', '32' ])
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| /qemu/target/microblaze/ |
| H A D | meson.build | 1 gen = decodetree.process('insns.decode')
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| /qemu/target/hppa/ |
| H A D | meson.build | 1 gen = decodetree.process('insns.decode')
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| /qemu/target/loongarch/ |
| H A D | meson.build | 1 gen = decodetree.process('insns.decode')
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| /qemu/target/openrisc/ |
| H A D | meson.build | 1 gen = decodetree.process('insns.decode')
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| /qemu/target/arm/tcg/ |
| H A D | neon-dp.decode | 48 # For FP insns the high bit of 'size' is used as part of opcode decode,
51 # integer neon insns use.
91 # the case for shifts. In the Arm ARM these insns are documented
94 # Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose
395 # patterns. This allows us to check that none of the insns within
403 # Miscellaneous size=0b11 insns
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| H A D | neon-shared.decode | 37 # For VCMLA/VCADD insns, convert the single-bit size field
40 # field in the 3same_fp Neon insns.)
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| H A D | a32-uncond.decode | 21 # All insns that have 0xf in insn[31:28] are decoded here.
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| H A D | vfp.decode | 1 # AArch32 VFP instruction descriptions (conditional insns)
88 # overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
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| H A D | mve.decode | 29 # 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit,
30 # like Neon FP insns.
84 # the case for shifts. In the Arm ARM these insns are documented
87 # Qd, Qm, Qn where other insns use Qd, Qn, Qm. For QEMU we choose
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| H A D | vfp-uncond.decode | 1 # AArch32 VFP instruction descriptions (unconditional insns)
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| H A D | t32.decode | 86 # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
726 # M-profile only: loop and branch insns
728 # All these BF insns have boff != 0b0000; we NOP them all
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| /qemu/tests/tcg/cris/bare/ |
| H A D | check_movpr.s | 4 # Test generic "move Ps,Rd" and "move Rs,Pd" insns; the ones with
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| H A D | check_movmp.s | 4 # Test generic "move Ps,[]" and "move [],Pd" insns; the ones with
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| /qemu/target/sparc/ |
| H A D | meson.build | 1 gen = decodetree.process('insns.decode')
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| /qemu/target/riscv/ |
| H A D | insn32.decode | 351 # Vector unit-stride load/store insns.
361 # Vector unit-stride mask load/store insns.
365 # Vector strided insns.
375 # Vector ordered-indexed and unordered-indexed load insns.
381 # Vector ordered-indexed and unordered-indexed store insns.
387 # Vector unit-stride fault-only-first load insns.
393 # Vector whole register insns
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| /qemu/include/hw/arm/ |
| H A D | boot.h | 232 const ARMInsnFixup *insns,
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| /qemu/linux-user/sparc/ |
| H A D | signal.c | 71 uint32_t insns[2] QEMU_ALIGNED(8); member
89 uint32_t insns[2]; member
303 install_sigtramp(sf->insns, TARGET_NR_sigreturn); in setup_frame()
366 install_sigtramp(sf->insns, TARGET_NR_rt_sigreturn); in setup_rt_frame()
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| /qemu/hw/arm/ |
| H A D | boot.c | 135 const ARMInsnFixup *insns, in arm_write_bootloader() argument
147 while (insns[len].fixup != FIXUP_TERMINATOR) { in arm_write_bootloader()
154 uint32_t insn = insns[i].insn; in arm_write_bootloader()
155 FixupType fixup = insns[i].fixup; in arm_write_bootloader()
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| /qemu/include/qemu/ |
| H A D | plugin.h | 133 GPtrArray *insns; member
|