/qemu/hw/pci/ |
H A D | pcie_doe.c | 100 if (intr && (msi_present(dev) || msix_present(dev))) { in pcie_doe_init() 101 doe_cap->cap.intr = intr; in pcie_doe_init() 169 if (doe_cap->cap.intr && doe_cap->ctrl.intr) { in pcie_doe_irq_assert() 170 if (doe_cap->status.intr) { in pcie_doe_irq_assert() 173 doe_cap->status.intr = 1; in pcie_doe_irq_assert() 265 doe_cap->cap.intr); in pcie_doe_read_config() 271 doe_cap->ctrl.intr); in pcie_doe_read_config() 276 doe_cap->status.intr); in pcie_doe_read_config() 329 doe_cap->ctrl.intr = 1; in pcie_doe_write_config() 332 doe_cap->ctrl.intr = 0; in pcie_doe_write_config() [all …]
|
/qemu/hw/usb/ |
H A D | hcd-xhci-pci.c | 46 if (enable == !!xhci->intr[n].msix_used) { in xhci_pci_intr_update() 52 xhci->intr[n].msix_used = true; in xhci_pci_intr_update() 56 xhci->intr[n].msix_used = false; in xhci_pci_intr_update() 95 int intr; in xhci_pci_vmstate_post_load() local 97 for (intr = 0; intr < s->xhci.numintrs; intr++) { in xhci_pci_vmstate_post_load() 98 if (s->xhci.intr[intr].msix_used) { in xhci_pci_vmstate_post_load() 99 msix_vector_use(pci_dev, intr); in xhci_pci_vmstate_post_load() 101 msix_vector_unuse(pci_dev, intr); in xhci_pci_vmstate_post_load()
|
H A D | hcd-xhci.c | 617 XHCIInterrupter *intr = &xhci->intr[v]; in xhci_write_event() local 634 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; in xhci_write_event() 643 if (intr->er_ep_idx >= intr->er_size) { in xhci_write_event() 645 intr->er_pcs = !intr->er_pcs; in xhci_write_event() 659 intr = &xhci->intr[v]; in xhci_event() 661 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); in xhci_event() 666 v, intr->er_start, intr->er_size); in xhci_event() 807 XHCIInterrupter *intr = &xhci->intr[v]; in xhci_er_reset() local 846 v, intr->er_start, intr->er_size); in xhci_er_reset() 3034 XHCIInterrupter *intr = &xhci->intr[v]; in xhci_runtime_read() local [all …]
|
H A D | tusb6010.c | 53 uint32_t intr; member 259 s->intr |= TUSB_INT_SRC_USB_IP_TX; in tusb_usbip_intr_update() 261 s->intr &= ~TUSB_INT_SRC_USB_IP_TX; in tusb_usbip_intr_update() 265 s->intr |= TUSB_INT_SRC_USB_IP_RX; in tusb_usbip_intr_update() 400 return s->intr; in tusb_async_readw() 591 s->intr |= value; in tusb_async_writew() 595 s->intr &= ~value; in tusb_async_writew() 692 s->intr |= TUSB_INT_SRC_OTG_TIMEOUT; in tusb_otg_tick() 747 s->intr |= 1 << source; in tusb_musb_core_intr() 749 s->intr &= ~(1 << source); in tusb_musb_core_intr() [all …]
|
H A D | hcd-dwc2.c | 83 if (!(s->gintsts & intr)) { in dwc2_raise_global_irq() 84 s->gintsts |= intr; in dwc2_raise_global_irq() 85 trace_usb_dwc2_raise_global_irq(intr); in dwc2_raise_global_irq() 92 if (s->gintsts & intr) { in dwc2_lower_global_irq() 93 s->gintsts &= ~intr; in dwc2_lower_global_irq() 358 intr |= pintr[stsidx]; in dwc2_handle_packet() 367 s->hreg1[index + 2] |= intr; in dwc2_handle_packet() 370 intr |= HCINTMSK_CHHLTD; in dwc2_handle_packet() 380 if (!(intr & HCINTMSK_CHHLTD)) { in dwc2_handle_packet() 383 intr &= ~HCINTMSK_RESERVED14_31; in dwc2_handle_packet() [all …]
|
H A D | dev-hub.c | 47 USBEndpoint *intr; member 223 usb_wakeup(s->intr, 0); in usb_hub_port_update_timer() 234 usb_wakeup(s->intr, 0); in usb_hub_attach() 243 usb_wakeup(s->intr, 0); in usb_hub_detach() 251 usb_wakeup(s->intr, 0); in usb_hub_detach() 268 usb_wakeup(s->intr, 0); in usb_hub_wakeup() 426 usb_wakeup(s->intr, 0); in usb_hub_handle_control() 611 s->intr = usb_ep_get(dev, USB_TOKEN_IN, 1); in usb_hub_realize()
|
H A D | hcd-ohci.c | 51 uint32_t intr[32]; member 266 if ((ohci->intr & OHCI_INTR_MIE) && in ohci_intr_update() 276 ohci->intr_status |= intr; in ohci_set_interrupt() 348 ohci->intr = OHCI_INTR_MIE; in ohci_soft_reset() 1543 retval = ohci->intr; in ohci_mem_read() 1681 ohci->intr |= val; in ohci_mem_write() 1686 ohci->intr &= ~val; in ohci_mem_write() 1845 uint32_t intr = 0; in ohci_wakeup() local 1850 intr = OHCI_INTR_RHSC; in ohci_wakeup() 1858 intr = OHCI_INTR_RD; in ohci_wakeup() [all …]
|
H A D | dev-wacom.c | 44 USBEndpoint *intr; member 201 usb_wakeup(s->intr, 0); in usb_mouse_event() 215 usb_wakeup(s->intr, 0); in usb_wacom_event() 414 s->intr = usb_ep_get(dev, USB_TOKEN_IN, 1); in usb_wacom_realize()
|
H A D | hcd-xhci.h | 138 uint16_t intr; member 218 XHCIInterrupter intr[XHCI_MAXINTRS]; member
|
H A D | hcd-uhci.c | 293 if (((s->status2 & 1) && (s->intr & (1 << 2))) || in uhci_update_irq() 294 ((s->status2 & 2) && (s->intr & (1 << 3))) || in uhci_update_irq() 295 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || in uhci_update_irq() 296 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || in uhci_update_irq() 321 s->intr = 0; in uhci_reset() 371 VMSTATE_UINT16(intr, UHCIState), 435 s->intr = val; in uhci_port_write() 498 val = s->intr; in uhci_port_read()
|
H A D | hcd-uhci.h | 51 uint16_t intr; /* interrupt enable register */ member
|
H A D | hcd-ohci.h | 54 uint32_t intr; member
|
/qemu/hw/pci-host/ |
H A D | xilinx-pcie.c | 68 s->intr |= set; in xilinx_pcie_update_intr() 69 s->intr &= ~clear; in xilinx_pcie_update_intr() 72 s->intr |= ROOTCFG_INTMASK_INTX; in xilinx_pcie_update_intr() 75 level = !!(s->intr & s->intr_mask); in xilinx_pcie_update_intr() 82 XilinxPCIEInt *intr; in xilinx_pcie_queue_intr() local 91 intr = &s->intr_fifo[s->intr_fifo_w]; in xilinx_pcie_queue_intr() 94 intr->fifo_reg1 = fifo_reg1; in xilinx_pcie_queue_intr() 95 intr->fifo_reg2 = fifo_reg2; in xilinx_pcie_queue_intr() 197 val = s->intr; in xilinx_pcie_root_config_read()
|
H A D | designware.c | 90 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; in designware_pcie_root_msi_write() 92 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { in designware_pcie_root_msi_write() 112 const bool enable = root->msi.intr[0].enable; in designware_pcie_root_update_msi_mapping() 164 val = root->msi.intr[0].enable; in designware_pcie_root_config_read() 168 val = root->msi.intr[0].mask; in designware_pcie_root_config_read() 172 val = root->msi.intr[0].status; in designware_pcie_root_config_read() 327 root->msi.intr[0].enable = val; in designware_pcie_root_config_write() 332 root->msi.intr[0].mask = val; in designware_pcie_root_config_write() 336 root->msi.intr[0].status ^= val; in designware_pcie_root_config_write() 337 if (!root->msi.intr[0].status) { in designware_pcie_root_config_write() [all …]
|
/qemu/include/hw/pci/ |
H A D | pcie_doe.h | 81 bool intr; member 87 bool intr; member 93 bool intr; member 112 DOEProtocol *protocols, bool intr, uint16_t vec);
|
/qemu/target/mips/ |
H A D | kvm.c | 138 struct kvm_mips_interrupt intr; in kvm_arch_pre_run() local 144 intr.cpu = -1; in kvm_arch_pre_run() 145 intr.irq = 2; in kvm_arch_pre_run() 195 struct kvm_mips_interrupt intr; in kvm_mips_set_interrupt() local 199 intr.cpu = -1; in kvm_mips_set_interrupt() 202 intr.irq = irq; in kvm_mips_set_interrupt() 204 intr.irq = -irq; in kvm_mips_set_interrupt() 220 intr.cpu = dest_cs->cpu_index; in kvm_mips_set_ipi_interrupt() 223 intr.irq = irq; in kvm_mips_set_ipi_interrupt() 225 intr.irq = -irq; in kvm_mips_set_ipi_interrupt() [all …]
|
/qemu/hw/remote/ |
H A D | proxy.c | 36 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &dev->intr, dev->virq); in proxy_intx_update() 45 kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &dev->intr, in proxy_intx_update() 56 event_notifier_init(&dev->intr, 0); in setup_irqfd() 62 msg.fds[0] = event_notifier_get_fd(&dev->intr); in setup_irqfd() 140 event_notifier_cleanup(&dev->intr); in pci_proxy_dev_exit()
|
/qemu/hw/input/ |
H A D | tsc210x.c | 101 int intr; member 214 s->kb.intr = 0; in tsc210x_reset() 363 if (s->kb.intr && (s->kb.mode & 2)) { in tsc2102_data_register_read() 364 s->kb.intr = 0; in tsc2102_data_register_read() 425 return (s->kb.intr << 15) | ((s->kb.scan || !s->kb.down) << 14) | in tsc2102_control_register_read() 587 if (s->kb.intr && s->kb.scan) { in tsc2102_control_register_write() 588 s->kb.intr = 0; in tsc2102_control_register_write() 1233 if (down && (s->kb.down & ~s->kb.mask) && !s->kb.intr) { in tsc210x_key_event() 1234 s->kb.intr = 1; in tsc210x_key_event() 1236 } else if (s->kb.intr && !(s->kb.down & ~s->kb.mask) && in tsc210x_key_event() [all …]
|
/qemu/hw/intc/ |
H A D | mips_gic.c | 263 int intr; in gic_write() local 300 intr = data & ~GIC_SH_WEDGE_RW_MSK; in gic_write() 302 OFFSET_CHECK(intr < gic->num_irq); in gic_write() 304 gic_set_irq(gic, intr, 1); in gic_write() 306 gic_set_irq(gic, intr, 0); in gic_write()
|
/qemu/hw/dma/ |
H A D | etraxfs_dma.c | 62 unsigned intr : 1; member 80 unsigned intr : 1; member 102 unsigned intr : 1; member 248 printf("intr=%x\n", (uint32_t) d->intr); in dump_d() 460 if (ctrl->channels[c].current_d.intr) { in channel_out_run() 527 if (ctrl->channels[c].current_d.intr) { in channel_in_process()
|
/qemu/include/hw/remote/ |
H A D | proxy.h | 43 EventNotifier intr; member
|
/qemu/include/hw/pci-host/ |
H A D | xilinx-pcie.h | 58 uint32_t intr; member
|
H A D | designware.h | 62 DesignwarePCIEMSIBank intr[DESIGNWARE_PCIE_NUM_MSI_BANKS]; member
|
/qemu/hw/i2c/ |
H A D | trace-events | 31 …st char *cmd_flags, uint32_t count, uint32_t intr_status) "handling cmd=0x%x %s count=%d intr=0x%x" 32 aspeed_i2c_bus_raise_interrupt(uint32_t intr_status, const char *s) "handled intr=0x%x %s"
|
/qemu/hw/block/ |
H A D | onenand.c | 56 qemu_irq intr; member 140 qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1); in onenand_intr_update() 566 qemu_irq_pulse(s->intr); in onenand_command() 825 sysbus_init_irq(sbd, &s->intr); in onenand_realize()
|