/qemu/linux-user/alpha/ |
H A D | cpu_loop.c | 75 trapnr = env->ir[IR_V0]; in cpu_loop() 77 env->ir[IR_A0], env->ir[IR_A1], in cpu_loop() 78 env->ir[IR_A2], env->ir[IR_A3], in cpu_loop() 79 env->ir[IR_A4], env->ir[IR_A5], in cpu_loop() 91 trapnr = (env->ir[IR_V0] != 0 && sysret < 0); in cpu_loop() 92 env->ir[IR_V0] = (trapnr ? -sysret : sysret); in cpu_loop() 93 env->ir[IR_A3] = trapnr; in cpu_loop() 113 switch (env->ir[IR_A0]) { in cpu_loop() 181 env->ir[i] = ((abi_ulong *)regs)[i]; in target_cpu_copy_regs() 183 env->ir[IR_SP] = regs->usp; in target_cpu_copy_regs()
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H A D | signal.c | 80 __put_user(env->ir[i], &sc->sc_regs[i]); in setup_sigcontext() 154 env->ir[IR_RA] = r26; in setup_frame() 155 env->ir[IR_PV] = env->pc = ka->_sa_handler; in setup_frame() 156 env->ir[IR_A0] = sig; in setup_frame() 157 env->ir[IR_A1] = 0; in setup_frame() 159 env->ir[IR_SP] = frame_addr; in setup_frame() 201 env->ir[IR_RA] = r26; in setup_rt_frame() 203 env->ir[IR_A0] = sig; in setup_rt_frame() 206 env->ir[IR_SP] = frame_addr; in setup_rt_frame() 212 abi_ulong sc_addr = env->ir[IR_A0]; in do_sigreturn() [all …]
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H A D | target_cpu.h | 26 env->ir[IR_SP] = newsp; in cpu_clone_regs_child() 28 env->ir[IR_V0] = 0; in cpu_clone_regs_child() 29 env->ir[IR_A3] = 0; in cpu_clone_regs_child() 30 env->ir[IR_A4] = 1; /* OSF/1 secondary return: child */ in cpu_clone_regs_child() 41 env->ir[IR_A4] = 0; in cpu_clone_regs_parent() 52 return state->ir[IR_SP]; in get_sp_from_cpustate()
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/qemu/hw/timer/ |
H A D | imx_gpt.c | 70 VMSTATE_UINT32(ir, IMXGPTState), 157 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { in imx_gpt_update_int() 214 if (s->ir & GPT_IR_OF1IE) { in imx_gpt_compute_next_timeout() 217 if (s->ir & GPT_IR_OF2IE) { in imx_gpt_compute_next_timeout() 220 if (s->ir & GPT_IR_OF3IE) { in imx_gpt_compute_next_timeout() 227 if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { in imx_gpt_compute_next_timeout() 230 if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { in imx_gpt_compute_next_timeout() 233 if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { in imx_gpt_compute_next_timeout() 282 reg_value = s->ir; in imx_gpt_read() 345 s->ir = 0; in imx_gpt_reset_common() [all …]
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/qemu/hw/intc/ |
H A D | rx_icu.c | 126 icu->ir[n_IRQ] = 0; in rxicu_set_irq() 135 icu->ir[n_IRQ] = 1; in rxicu_set_irq() 153 icu->ir[n_IRQ] = 0; in rxicu_ack_irq() 159 if (icu->ir[i]) { in rxicu_ack_irq() 186 return icu->ir[reg] & R_IR_IR_MASK; in icu_read() 235 icu->ir[reg] = 0; in icu_write() 349 VMSTATE_UINT8_ARRAY(ir, RXICUState, NR_IRQS),
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H A D | ppc-uic.c | 54 uint32_t ir, cr; in ppcuic_trigger_irq() local 58 ir = uic->uicsr & uic->uicer & (~uic->uiccr); in ppcuic_trigger_irq() 64 uic->uicsr & uic->uicer, ir, cr); in ppcuic_trigger_irq() 65 if (ir != 0x0000000) { in ppcuic_trigger_irq()
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/qemu/target/alpha/ |
H A D | translate.c | 69 TCGv *ir; member 191 return ctx->ir[reg]; in load_gpr() 203 return ctx->ir[reg]; in load_gpr_lit() 212 return ctx->ir[reg]; in dest_gpr() 345 dest = ctx->ir[ra]; in gen_load_int() 432 tcg_gen_movi_i64(ctx->ir[ra], 0); in gen_store_conditional() 461 gen_pc_disp(ctx, ctx->ir[ra], 0); in gen_bdirect() 1053 tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env, in gen_call_pal() 1139 tcg_gen_movi_i64(ctx->ir[IR_V0], 0); in gen_call_pal() 2364 gen_pc_disp(ctx, ctx->ir[ra], 0); in translate_one() [all …]
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H A D | machine.c | 28 VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31),
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H A D | helper.c | 110 return &env->ir[reg]; in cpu_alpha_addr_gr() 372 env->pc, env->ir[IR_SP]); in alpha_cpu_do_interrupt()
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H A D | cpu.h | 199 uint64_t ir[31]; member
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/qemu/target/cris/ |
H A D | translate_v10.c.inc | 205 imm = dc->ir & ((1 << 6) - 1); 213 simm = (int8_t)dc->ir; 308 imm = dc->ir & 0xff; 335 flags = EXTRACT_FIELD(dc->ir, 0, 3) 426 if (dc->ir & 32) 443 if (dc->ir & 32) 946 if (!dc->postinc && (dc->ir & (1 << 11))) { 947 int simm = dc->ir & 0xff; 1176 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0); 1179 dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9); [all …]
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H A D | translate.c | 99 uint32_t ir; member 1198 offset = EXTRACT_FIELD(dc->ir, 1, 7); in dec_bccq() 1199 sign = EXTRACT_FIELD(dc->ir, 0, 0); in dec_bccq() 1216 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7); in dec_addoq() 1231 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); in dec_addq() 1244 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); in dec_moveq() 1254 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); in dec_subq() 1268 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); in dec_cmpq() 1283 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); in dec_andq() 1865 | EXTRACT_FIELD(dc->ir, 0, 3); in dec_setclrf() [all …]
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/qemu/include/hw/intc/ |
H A D | rx_icu.h | 57 uint8_t ir[NR_IRQS]; member
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/qemu/include/hw/timer/ |
H A D | imx_gpt.h | 102 uint32_t ir; member
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/qemu/hw/ppc/ |
H A D | ppc405.h | 87 uint32_t ir; member
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H A D | trace-events | 122 ppc4xx_fit(uint32_t ir, uint64_t tcr, uint64_t tsr) "ir %d TCR 0x%" PRIx64 " TSR 0x%" PRIx64 125 ppc4xx_pit(uint32_t ar, uint32_t ir, uint64_t tcr, uint64_t tsr, uint64_t reload) "ar %d ir %d TCR …
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/qemu/hw/isa/ |
H A D | lpc_ich9.c | 65 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) in ich9_cc_update_ir() argument 69 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; in ich9_cc_update_ir()
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/qemu/target/microblaze/ |
H A D | translate.c | 1629 uint32_t ir; in mb_tr_translate_insn() local 1639 ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next); in mb_tr_translate_insn() 1640 if (!decode(dc, ir)) { in mb_tr_translate_insn()
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/qemu/target/rx/ |
H A D | translate.c | 1449 static inline void rx_rot(int ir, int dir, int rd, int src) in rx_rot() argument 1453 if (ir == ROT_IMM) { in rx_rot() 1461 if (ir == ROT_IMM) { in rx_rot()
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/qemu/linux-user/ |
H A D | syscall.c | 1599 cpu_env->ir[IR_A4] = host_pipe[1]; in do_pipe() 9401 cpu_env->ir[IR_A4] = getppid(); in _syscall2() 9987 cpu_env->ir[IR_V0] = 0; /* force no error */ in _syscall2() 10586 cpu_env->ir[IR_V0] = 0; in _syscall2() 11983 cpu_env->ir[IR_A4]=euid; in _syscall2() 11993 cpu_env->ir[IR_A4]=egid; in _syscall2()
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