Home
last modified time | relevance | path

Searched refs:irr (Results 1 – 24 of 24) sorted by relevance

/qemu/hw/intc/
H A Di8259.c82 mask = s->irr & ~s->imr; in pic_get_irq()
113 trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); in pic_update_irq()
139 s->irr |= mask; in pic_set_irq()
142 s->irr &= ~mask; in pic_set_irq()
149 s->irr |= mask; in pic_set_irq()
171 s->irr &= ~(1 << irq); in pic_intack()
344 ret = s->irr; in pic_ioport_read()
H A Dioapic.c101 if (s->irr & mask) { in ioapic_service()
108 s->irr &= ~mask; in ioapic_service()
174 s->irr |= mask; in ioapic_set_irq()
179 s->irr &= ~mask; in ioapic_set_irq()
185 s->irr |= mask; in ioapic_set_irq()
270 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { in ioapic_eoi_broadcast()
H A Dioapic_common.c113 ioapic_irr_dump(mon, " IRR", s->irr); in ioapic_print_redtbl()
124 s->irr = 0; in ioapic_reset_common()
193 VMSTATE_UINT32_V(irr, IOAPICCommonState, 2),
H A Dapic.c133 vector = get_highest_priority_int(s->irr); in apic_sync_vapic()
137 vapic_state.irr = vector & 0xff; in apic_sync_vapic()
196 apic_reset_bit(s->irr, lvt & 0xff); in apic_deliver_pic_intr()
400 return get_highest_priority_int(s->irr); in apic_get_highest_priority_irr()
445 irrv = get_highest_priority_int(s->irr); in apic_irq_pending()
483 kvm_report_irq_delivered(!apic_get_bit(s->irr, vector_num)); in apic_set_irq()
485 apic_set_bit(s->irr, vector_num); in apic_set_irq()
748 apic_reset_bit(s->irr, intno); in apic_get_interrupt()
857 val = s->irr[index & 7]; in apic_register_read()
H A Di8259_common.c40 s->irr &= s->elcr; in pic_reset_common()
142 s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add, in pic_print_info()
173 VMSTATE_UINT8(irr, PICCommonState),
H A Dapic_common.c212 memset(s->irr, 0, sizeof(s->irr)); in apic_init_reset()
392 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
H A Dioapic_internal.h104 uint32_t irr; member
H A Dtrace-events4 pic_update_irq(bool master, uint8_t imr, uint8_t irr, uint8_t padd) "master %d imr %"PRIu8" irr %"P…
21 ioapic_set_remote_irr(int n) "set remote irr for pin %d"
22 ioapic_clear_remote_irr(int n, int vector) "clear remote irr for pin %d vector %d"
/qemu/hw/i386/kvm/
H A Dioapic.c73 s->irr = kioapic->irr; in kvm_ioapic_get()
91 kioapic->irr = s->irr; in kvm_ioapic_put()
H A Di8259.c53 s->irr = kpic->irr; in kvm_pic_get()
81 kpic->irr = s->irr; in kvm_pic_put()
H A Dapic.c50 kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]); in kvm_put_apic_state()
80 s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i); in kvm_get_apic_state()
/qemu/hw/gpio/
H A Dzaurus.c47 uint16_t irr; member
95 return s->irr; in scoop_read()
137 s->irr = value; in scoop_write()
238 VMSTATE_UINT16(irr, ScoopInfo),
/qemu/hw/misc/
H A Dlasi.c65 val = s->irr; in lasi_chip_read_with_attrs()
213 VMSTATE_UINT32(irr, LasiState),
235 s->irr |= bit; in lasi_set_irq()
/qemu/hw/isa/
H A Dlpc_ich9.c65 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) in ich9_cc_update_ir()
69 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; in ich9_cc_update_ir()
94 ich9_cc_update_ir(lpc->irr[slot], in ich9_cc_update()
105 lpc->irr[30][pci_intx] = pci_intx + 4; in ich9_cc_update()
125 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; in ich9_cc_init()
283 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; in ich9_lpc_map_irq()
/qemu/include/hw/i386/
H A Dapic_internal.h173 uint32_t irr[8]; /* interrupt request register */ member
199 uint8_t irr; member
/qemu/include/hw/misc/
H A Dlasi.h66 uint32_t irr; member
/qemu/target/i386/hvf/
H A Dhvf.c82 int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); in vmx_update_tpr() local
85 if (irr == -1) { in vmx_update_tpr()
88 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : in vmx_update_tpr()
89 irr >> 4); in vmx_update_tpr()
/qemu/include/hw/isa/
H A Di8259_internal.h48 uint8_t irr; /* interrupt request register */ member
/qemu/target/i386/whpx/
H A Dwhpx-apic.c45 kapic->fields[0x20 + i].data = s->irr[i]; in whpx_put_apic_state()
73 s->irr[i] = kapic->fields[0x20 + i].data; in whpx_get_apic_state()
/qemu/include/hw/southbridge/
H A Dich9.h32 uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; member
/qemu/linux-headers/asm-x86/
H A Dkvm.h60 __u8 irr; /* interrupt request register */ member
82 __u32 irr; member
/qemu/hw/audio/
H A Dintel-hda.c177 uint32_t irr; member
354 d->irr = response; in intel_hda_response()
796 .offset = offsetof(IntelHDAState, irr),
1204 VMSTATE_UINT32(irr, IntelHDAState),
/qemu/pc-bios/optionrom/
H A Dkvmvapic.S17 # stale tpr/isr/irr data to corrupt the vapic area.
/qemu/target/i386/
H A Dcpu-dump.c327 dump_apic_interrupt("IRR", s->irr, s->tmr); in x86_cpu_dump_local_apic_state()