Searched refs:mdscr_el1 (Results 1 – 5 of 5) sorted by relevance
/qemu/target/arm/ |
H A D | debug_helper.c | 87 return extract32(env->cp15.mdscr_el1, 13, 1) in aa64_generate_debug_exceptions() 167 return extract32(env->cp15.mdscr_el1, 0, 1) in arm_singlestep_active() 364 if (extract32(env->cp15.mdscr_el1, 15, 1) == 0 in check_watchpoints() 388 if (extract32(env->cp15.mdscr_el1, 15, 1) == 0 in arm_debug_check_breakpoint() 869 bool mdscr_el1_tdcc = extract32(env->cp15.mdscr_el1, 12, 1); in access_tdcc() 964 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), 1012 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
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H A D | cpu.h | 475 uint64_t mdscr_el1; member
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H A D | cpu.c | 313 env->cp15.mdscr_el1 |= 1 << 12; in arm_cpu_reset_hold()
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H A D | helper.c | 11274 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); in arm_cpu_do_interrupt_aarch32()
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/qemu/target/arm/hvf/ |
H A D | hvf.c | 1595 env->cp15.mdscr_el1 = val; in hvf_sysreg_write() 2230 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug() 2231 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1); in hvf_arch_update_guest_debug() 2234 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug() 2235 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0); in hvf_arch_update_guest_debug() 2240 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug() 2241 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1); in hvf_arch_update_guest_debug() 2243 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug() 2244 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0); in hvf_arch_update_guest_debug()
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