/qemu/hw/pci-host/ |
H A D | pnv_phb3_msi.c | 102 ICSState *ics = ICS(msi); in phb3_msi_try_send() 161 ICSState *ics = ICS(msi); in pnv_phb3_msi_send() 203 msi->rba[idx] |= bit; in phb3_msi_reject() 212 if (msi->rba_sum == 0) { in phb3_msi_resend() 240 memset(msi->rba, 0, sizeof(msi->rba)); in phb3_msi_reset_hold() 241 msi->rba_sum = 0; in phb3_msi_reset_hold() 247 ICSState *ics = ICS(msi); in pnv_phb3_msi_update_config() 259 ICSState *ics = ICS(msi); in phb3_msi_realize() 263 assert(msi->phb); in phb3_msi_realize() 271 msi->qirqs = qemu_allocate_irqs(phb3_msi_set_irq, msi, ics->nr_irqs); in phb3_msi_realize() [all …]
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H A D | designware.c | 90 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; in designware_pcie_root_msi_write() 92 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { in designware_pcie_root_msi_write() 156 val = root->msi.base; in designware_pcie_root_config_read() 160 val = root->msi.base >> 32; in designware_pcie_root_config_read() 164 val = root->msi.intr[0].enable; in designware_pcie_root_config_read() 168 val = root->msi.intr[0].mask; in designware_pcie_root_config_read() 172 val = root->msi.intr[0].status; in designware_pcie_root_config_read() 316 root->msi.base |= val; in designware_pcie_root_config_write() 327 root->msi.intr[0].enable = val; in designware_pcie_root_config_write() 332 root->msi.intr[0].mask = val; in designware_pcie_root_config_write() [all …]
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/qemu/hw/xen/ |
H A D | xen_pt_msi.c | 71 return (uint64_t)msi->addr_hi << 32 | msi->addr_lo; in msi_addr64() 240 if (!s->msi) { in xen_pt_msi_set_enable() 253 XenPTMSI *msi = s->msi; in xen_pt_msi_setup() local 261 rc = msi_msix_setup(s, msi_addr64(msi), msi->data, &pirq, false, 0, true); in xen_pt_msi_setup() 271 msi->pirq = pirq; in xen_pt_msi_setup() 279 XenPTMSI *msi = s->msi; in xen_pt_msi_update() local 282 return msi_msix_update(s, msi_addr64(msi), msi->data, msi->pirq, in xen_pt_msi_update() 283 false, 0, &msi->pirq, msi->mask & 1); in xen_pt_msi_update() 288 XenPTMSI *msi = s->msi; in xen_pt_msi_disable() local 290 if (!msi) { in xen_pt_msi_disable() [all …]
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H A D | xen_pt_config_init.c | 1076 XenPTMSI *msi = s->msi; in xen_pt_msgctrl_reg_init() local 1090 msi->flags |= reg_field; in xen_pt_msgctrl_reg_init() 1093 msi->mapped = false; in xen_pt_msgctrl_reg_init() 1103 XenPTMSI *msi = s->msi; in xen_pt_msgctrl_reg_write() local 1236 s->msi->addr_lo = *data; in xen_pt_msgaddr32_reg_write() 1271 s->msi->addr_hi = *data; in xen_pt_msgaddr64_reg_write() 1294 XenPTMSI *msi = s->msi; in xen_pt_msgdata_reg_write() local 1311 msi->data = *data; in xen_pt_msgdata_reg_write() 1318 if (msi->mapped) { in xen_pt_msgdata_reg_write() 1337 s->msi->mask = *val; in xen_pt_mask_reg_write() [all …]
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/qemu/hw/intc/ |
H A D | arm_gicv3_its_kvm.c | 47 struct kvm_msi msi; in kvm_its_send_msi() local 59 msi.address_lo = extract64(s->gits_translater_gpa, 0, 32); in kvm_its_send_msi() 60 msi.address_hi = extract64(s->gits_translater_gpa, 32, 32); in kvm_its_send_msi() 61 msi.data = le32_to_cpu(value); in kvm_its_send_msi() 62 msi.flags = KVM_MSI_VALID_DEVID; in kvm_its_send_msi() 63 msi.devid = devid; in kvm_its_send_msi() 64 memset(msi.pad, 0, sizeof(msi.pad)); in kvm_its_send_msi() 66 return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); in kvm_its_send_msi()
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H A D | riscv_imsic.c | 289 struct kvm_msi msi; in riscv_imsic_write() local 291 msi.address_lo = extract64(imsic->mmio.addr + addr, 0, 32); in riscv_imsic_write() 292 msi.address_hi = extract64(imsic->mmio.addr + addr, 32, 32); in riscv_imsic_write() 293 msi.data = le32_to_cpu(value); in riscv_imsic_write() 295 kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); in riscv_imsic_write()
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H A D | apic.c | 921 static void apic_send_msi(MSIMessage *msi) in apic_send_msi() argument 923 uint64_t addr = msi->address; in apic_send_msi() 924 uint32_t data = msi->data; in apic_send_msi() 1090 MSIMessage msi = { .address = addr, .data = val }; in apic_mem_write() local 1091 apic_send_msi(&msi); in apic_mem_write()
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/qemu/hw/pci-bridge/ |
H A D | pci_bridge_dev.c | 50 OnOffAuto msi; member 75 bridge_dev->msi = ON_OFF_AUTO_OFF; in pci_bridge_dev_realize() 83 if (bridge_dev->msi != ON_OFF_AUTO_OFF) { in pci_bridge_dev_realize() 90 if (err && bridge_dev->msi == ON_OFF_AUTO_ON) { in pci_bridge_dev_realize() 97 assert(!local_err || bridge_dev->msi == ON_OFF_AUTO_AUTO); in pci_bridge_dev_realize() 175 DEFINE_PROP_ON_OFF_AUTO(PCI_BRIDGE_DEV_PROP_MSI, PCIBridgeDev, msi,
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H A D | pcie_pci_bridge.c | 26 OnOffAuto msi; member 71 if (pcie_br->msi != ON_OFF_AUTO_OFF) { in OBJECT_DECLARE_SIMPLE_TYPE() 75 if (pcie_br->msi != ON_OFF_AUTO_ON) { in OBJECT_DECLARE_SIMPLE_TYPE() 128 DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_AUTO),
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/qemu/hw/ppc/ |
H A D | spapr_pci.c | 282 SpaprPciMsi *msi; in rtas_ibm_change_msi() local 330 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); in rtas_ibm_change_msi() 334 if (!msi) { in rtas_ibm_change_msi() 408 if (msi) { in rtas_ibm_change_msi() 422 g_hash_table_insert(phb->msi, config_addr_key, msi); in rtas_ibm_change_msi() 448 SpaprPciMsi *msi; in rtas_ibm_query_interrupt_source_number() local 461 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); in rtas_ibm_query_interrupt_source_number() 462 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { in rtas_ibm_query_interrupt_source_number() 1816 spapr_irq_msi_free(spapr, msi->first_irq, msi->num); in spapr_phb_destroy_msi() 1818 spapr_irq_free(spapr, msi->first_irq, msi->num); in spapr_phb_destroy_msi() [all …]
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H A D | e500.c | 392 char *msi; in ppce500_load_device_tree() local 590 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); in ppce500_load_device_tree() 591 qemu_fdt_add_subnode(fdt, msi); in ppce500_load_device_tree() 592 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); in ppce500_load_device_tree() 593 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); in ppce500_load_device_tree() 595 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); in ppce500_load_device_tree() 596 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); in ppce500_load_device_tree() 597 qemu_fdt_setprop_cells(fdt, msi, "interrupts", in ppce500_load_device_tree() 606 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); in ppce500_load_device_tree() 607 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); in ppce500_load_device_tree() [all …]
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/qemu/hw/i386/xen/ |
H A D | xen_apic.c | 74 static void xen_send_msi(MSIMessage *msi) in xen_send_msi() argument 76 xen_hvm_inject_msi(msi->address, msi->data); in xen_send_msi()
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/qemu/scripts/ |
H A D | extract-vsssdk-headers | 29 tail -c +$(($offset+1)) -- "$1" > vsssdk.msi 32 msiextract -C $tmpdir vsssdk.msi
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/qemu/hw/usb/ |
H A D | hcd-xhci-pci.c | 128 if (s->msi != ON_OFF_AUTO_OFF) { in usb_xhci_pci_realize() 135 if (ret && s->msi == ON_OFF_AUTO_ON) { in usb_xhci_pci_realize() 142 assert(!err || s->msi == ON_OFF_AUTO_AUTO); in usb_xhci_pci_realize() 242 s->msi = ON_OFF_AUTO_OFF; in qemu_xhci_instance_init()
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H A D | hcd-xhci-pci.h | 41 OnOffAuto msi; member
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H A D | hcd-xhci-nec.c | 42 DEFINE_PROP_ON_OFF_AUTO("msi", XHCIPciState, msi, ON_OFF_AUTO_AUTO),
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/qemu/docs/system/i386/ |
H A D | kvm-pv.rst | 24 ``kvm-msi-ext-dest-id`` feature is enabled by default in x2apic mode with split 77 ``kvm-msi-ext-dest-id``
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/qemu/hw/audio/ |
H A D | intel-hda.c | 199 OnOffAuto msi; member 262 bool msi = msi_enabled(&d->pci); in intel_hda_update_irq() local 272 level, msi ? "msi" : "intx"); in intel_hda_update_irq() 273 if (msi) { in intel_hda_update_irq() 1104 if (d->msi != ON_OFF_AUTO_OFF) { in intel_hda_realize() 1110 if (ret && d->msi == ON_OFF_AUTO_ON) { in intel_hda_realize() 1117 assert(!err || d->msi == ON_OFF_AUTO_AUTO); in intel_hda_realize() 1220 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO),
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/qemu/pc-bios/ |
H A D | canyonlands.dts | 439 enable-msi-hole; 548 MSI: ppc4xx-msi@C10000000 { 549 compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; 552 msi-data = <0x00000000>; 553 msi-mask = <0x44440000>;
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/qemu/include/hw/pci-host/ |
H A D | designware.h | 75 DesignwarePCIEMSI msi; member
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H A D | spapr.h | 71 GHashTable *msi; member
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/qemu/hw/pci/ |
H A D | meson.build | 3 'msi.c',
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/qemu/accel/kvm/ |
H A D | kvm-all.c | 2025 struct kvm_msi msi; in kvm_irqchip_send_msi() local 2027 msi.address_lo = (uint32_t)msg.address; in kvm_irqchip_send_msi() 2028 msi.address_hi = msg.address >> 32; in kvm_irqchip_send_msi() 2029 msi.data = le32_to_cpu(msg.data); in kvm_irqchip_send_msi() 2030 msi.flags = 0; in kvm_irqchip_send_msi() 2031 memset(msi.pad, 0, sizeof(msi.pad)); in kvm_irqchip_send_msi() 2033 return kvm_vm_ioctl(s, KVM_SIGNAL_MSI, &msi); in kvm_irqchip_send_msi() 2064 kroute.u.msi.address_hi = msg.address >> 32; in kvm_irqchip_add_msi_route() 2065 kroute.u.msi.data = le32_to_cpu(msg.data); in kvm_irqchip_add_msi_route() 2107 kroute.u.msi.address_hi = msg.address >> 32; in kvm_irqchip_update_msi_route() [all …]
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/qemu/hw/scsi/ |
H A D | mptsas.h | 36 OnOffAuto msi; member
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/qemu/include/hw/ppc/ |
H A D | openpic.h | 169 OpenPICMSI msi[MAX_MSI]; member
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