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Searched refs:msr (Results 1 – 25 of 64) sorted by relevance

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/qemu/target/ppc/
H A Dexcp_helper.c295 bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1); in ppc_excp_apply_ail()
403 assert((msr & env->msr_mask) == msr); in powerpc_set_excp_state()
413 env->msr = msr; in powerpc_set_excp_state()
489 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_40x()
596 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_6xx()
739 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_7xx()
889 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_74xx()
1037 msr = env->msr; in powerpc_excp_booke()
1334 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_books()
2500 msr |= env->msr & (1ULL << MSR_SF); in ppc_cpu_do_fwnmi_machine_check()
[all …]
H A Dhelper_regs.c53 bool pr = !!(env->msr & (1 << MSR_PR)); in hreg_check_bhrb_enable()
68 hv = !!(env->msr & (1ull << MSR_HV)); in hreg_check_bhrb_enable()
131 target_ulong msr = env->msr; in hreg_compute_hflags_value() local
163 if (msr_is_64bit(env, msr)) { in hreg_compute_hflags_value()
219 dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1; in hreg_compute_hflags_value()
238 return hflags | (msr & msr_mask); in hreg_compute_hflags_value()
300 if (!alter_hv || !(env->msr & MSR_HVB)) { in hreg_store_msr()
302 value |= env->msr & MSR_HVB; in hreg_store_msr()
307 value |= env->msr & (1 << MSR_ME); in hreg_store_msr()
314 ((value ^ env->msr) & R_MSR_GS_MASK)) { in hreg_store_msr()
[all …]
H A Dmem_helper.c35 return FIELD_EX64(env->msr, MSR, LE); in needs_byteswap()
37 return !FIELD_EX64(env->msr, MSR, LE); in needs_byteswap()
48 if (!msr_is_64bit(env, env->msr)) { in addr_add()
394 if (FIELD_EX64(env->msr, MSR, LE)) { \
421 if (FIELD_EX64(env->msr, MSR, LE)) { \ in LVE()
455 if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \
486 if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \
522 (FIELD_EX64_HV(env->msr) << TEXASR_PRIVILEGE_HV) |
523 (FIELD_EX64(env->msr, MSR, PR) << TEXASR_PRIVILEGE_PR) |
526 env->spr[SPR_TFIAR] = env->nip | (FIELD_EX64_HV(env->msr) << 1) |
[all …]
H A Dmmu-booke.c79 pr = FIELD_EX64(env->msr, MSR, PR); in mmu40x_get_physical_address()
168 FIELD_EX64(env->msr, MSR, IR) : in mmubooke_check_tlb()
169 FIELD_EX64(env->msr, MSR, DR)) != (tlb->attr & 1)) { in mmubooke_check_tlb()
174 if (FIELD_EX64(env->msr, MSR, PR)) { in mmubooke_check_tlb()
226 if (!FIELD_EX64(env->msr, MSR, CM)) { in ppcmas_tlb_check()
302 *as_out = FIELD_EX64(env->msr, MSR, DS); in mmubooke206_get_as()
303 *pr_out = FIELD_EX64(env->msr, MSR, PR); in mmubooke206_get_as()
351 as = FIELD_EX64(env->msr, MSR, IR); in mmubooke206_check_tlb()
431 as = FIELD_EX64(env->msr, MSR, IR); in booke206_update_mas_tlb_miss()
H A Dtrace-events33 ppc_excp_rfi(uint64_t nip, uint64_t msr) "Return from exception at 0x%" PRIx64 " with flags 0x%016"…
35 ppc_excp_isi(uint64_t msr, uint64_t nip) "ISI exception: msr=0x%016" PRIx64 " nip=0x%" PRIx64
H A Dmachine.c16 target_ulong msr = env->msr; in post_load_update_msr() local
22 env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); in post_load_update_msr()
23 ppc_store_msr(env, msr); in post_load_update_msr()
440 return FIELD_EX64(env->msr, MSR, TS); in tm_needed()
758 VMSTATE_UINTTL(env.msr, PowerPCCPU),
H A Dmmu_common.c261 if ((!FIELD_EX64(env->msr, MSR, PR) && (*BATu & 0x00000002)) || in bat_size_prot()
262 (FIELD_EX64(env->msr, MSR, PR) && (*BATu & 0x00000001))) { in bat_size_prot()
365 pr = FIELD_EX64(env->msr, MSR, PR); in mmu6xx_get_physical_address()
380 (int)FIELD_EX64(env->msr, MSR, IR), in mmu6xx_get_physical_address()
381 (int)FIELD_EX64(env->msr, MSR, DR), pr ? 1 : 0, in mmu6xx_get_physical_address()
693 if (access_type == MMU_INST_FETCH ? !FIELD_EX64(env->msr, MSR, IR) in ppc_real_mode_xlate()
694 : !FIELD_EX64(env->msr, MSR, DR)) { in ppc_real_mode_xlate()
H A Darch_dump.c36 reg_t msr; member
118 reg->msr = cpu_to_dump_reg(s, cpu->env.msr); in ppc_write_elf_prstatus()
H A Dmmu-radix64.c41 if (FIELD_EX64(env->msr, MSR, HV)) { /* MSR[HV] -> Hypervisor/bare metal */ in ppc_radix64_get_fully_qualified_addr()
201 FIELD_EX64(env->msr, MSR, PR)) { in ppc_radix64_check_prot()
365 if (lpid == 0 && !FIELD_EX64(env->msr, MSR, HV)) { in validate_pate()
528 if (FIELD_EX64(env->msr, MSR, HV) || vhyp_flat_addressing(cpu)) { in ppc_radix64_process_scoped_xlate()
/qemu/tests/qtest/
H A Dfdc-test.c81 uint8_t msr; in floppy_send() local
84 assert_bit_set(msr, RQM); in floppy_send()
85 assert_bit_clear(msr, DIO); in floppy_send()
92 uint8_t msr; in floppy_recv() local
95 assert_bit_set(msr, RQM | DIO); in floppy_recv()
128 uint8_t msr = 0; in send_read_command() local
148 if (msr == 0xd0) { in send_read_command()
184 uint8_t msr = 0; in send_read_no_dma_command() local
241 assert_bit_set(msr, RQM); in send_read_no_dma_command()
415 uint8_t msr; in test_read_id() local
[all …]
/qemu/target/microblaze/
H A Dhelper.c108 uint32_t t, msr = mb_cpu_read_msr(env); in mb_cpu_do_interrupt() local
139 msr |= MSR_EIP; in mb_cpu_do_interrupt()
166 msr |= MSR_EIP; in mb_cpu_do_interrupt()
172 assert(msr & MSR_IE); in mb_cpu_do_interrupt()
181 msr &= ~MSR_IE; in mb_cpu_do_interrupt()
195 msr |= MSR_BIP; in mb_cpu_do_interrupt()
206 t = (msr & (MSR_VM | MSR_UM)) << 1; in mb_cpu_do_interrupt()
208 msr |= t; in mb_cpu_do_interrupt()
209 mb_cpu_write_msr(env, msr); in mb_cpu_do_interrupt()
259 && (env->msr & MSR_IE) in mb_cpu_exec_interrupt()
[all …]
H A Dmachine.c42 CPUMBState *env = container_of(opaque, CPUMBState, msr); in get_msr()
51 CPUMBState *env = container_of(opaque, CPUMBState, msr); in put_msr()
67 VMSTATE_SINGLE(msr, CPUMBState, 0, vmstate_msr, uint32_t),
H A Dcpu.h249 uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ member
387 return env->msr | (env->msr_c * (MSR_C | MSR_CC)); in mb_cpu_read_msr()
397 env->msr = val & ~(MSR_C | MSR_CC | MSR_PVR); in mb_cpu_write_msr()
419 *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); in cpu_get_tb_cpu_state()
H A Dop_helper.c76 env->msr |= MSR_DZ; in check_divz()
78 if ((env->msr & MSR_EE) && in check_divz()
139 && (env->msr & MSR_EE)) { in update_fpu_flags()
411 if (!(env->msr & MSR_EE)) { in mb_cpu_transaction_failed()
/qemu/scripts/kvm/
H A Dvmxcap28 class msr(object): class
49 m = msr()
78 m = msr()
83 def __init__(self, name, bits, msr): argument
86 self.msr = msr
89 value = msr().read(self.msr, 0)
120 msr = MSR_IA32_VMX_BASIC,
262 msr = MSR_IA32_VMX_MISC_CTLS,
286 msr = MSR_IA32_VMX_EPT_VPID_CAP,
293 msr = MSR_IA32_VMX_VMFUNC,
/qemu/hw/char/
H A Dserial.c198 omsr = s->msr; in serial_update_msl()
200 s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; in serial_update_msl()
201 s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; in serial_update_msl()
202 s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; in serial_update_msl()
203 s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; in serial_update_msl()
205 if (s->msr != omsr) { in serial_update_msl()
207 s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); in serial_update_msl()
210 s->msr &= ~UART_MSR_TERI; in serial_update_msl()
539 ret = s->msr; in serial_ioport_read()
542 s->msr &= 0xF0; in serial_ioport_read()
[all …]
/qemu/tests/tcg/aarch64/system/
H A Dboot.S92 msr vbar_el1, x0
97 msr ttbr0_el1, x0
156 msr tcr_el1, x0
159 msr mair_el1, x0
178 msr sctlr_el1, x0
189 msr cpacr_el1, x0
/qemu/target/i386/kvm/
H A Dkvm_i386.h69 typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val);
70 typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val);
72 uint32_t msr; member
77 bool kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
H A Dhyperv.c63 switch (exit->u.synic.msr) { in kvm_hv_handle_exit()
121 switch (exit->u.syndbg.msr) { in kvm_hv_handle_exit()
H A Dkvm.c2643 ret = kvm_xen_init(s, msr); in kvm_arch_init()
3926 uint32_t msr; in kvm_get_msrs() local
3931 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) { in kvm_get_msrs()
3936 uint32_t msr; in kvm_get_msrs() local
3938 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT; in kvm_get_msrs()
3939 msr++) { in kvm_get_msrs()
5204 if (handler->msr) { in kvm_install_msr_filters()
5240 .msr = msr, in kvm_filter_msr()
5264 if (run->msr.index == handler->msr) { in kvm_handle_rdmsr()
5284 if (run->msr.index == handler->msr) { in kvm_handle_wrmsr()
[all …]
/qemu/hw/block/
H A Dfdc.c1036 VMSTATE_UINT8(msr, FDCtrl),
1106 fdctrl->msr = FD_MSR_RQM; in fdctrl_reset()
1281 uint32_t retval = fdctrl->msr; in fdctrl_read_main_status()
1357 fdctrl->msr |= FD_MSR_RQM; in fdctrl_to_command_phase()
1457 fdctrl->msr &= ~FD_MSR_NONDMA; in fdctrl_stop_transfer()
1555 fdctrl->msr &= ~FD_MSR_RQM; in fdctrl_start_transfer()
1573 fdctrl->msr |= FD_MSR_DIO; in fdctrl_start_transfer()
1599 if (fdctrl->msr & FD_MSR_RQM) { in fdctrl_transfer_handler()
1722 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { in fdctrl_read_data()
2218 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { in fdctrl_write_data()
[all …]
/qemu/linux-user/ppc/
H A Dsignal.c245 target_ulong msr = env->msr; in save_user_regs() local
316 __put_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); in save_user_regs()
330 target_ulong msr; in restore_user_regs() local
357 __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); in restore_user_regs()
361 ppc_store_msr(env, ((env->msr & ~(1ull << MSR_LE)) | in restore_user_regs()
362 (msr & (1ull << MSR_LE)))); in restore_user_regs()
469 ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); in setup_frame()
558 ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); in setup_rt_frame()
561 ppc_store_msr(env, env->msr | (1ull << MSR_LE)); in setup_rt_frame()
H A Dtarget_syscall.h33 abi_ulong msr; member
H A Dcpu_loop.c388 ppc_store_msr(env, env->msr & ~((target_ulong)1 << flag)); in target_cpu_copy_regs()
390 ppc_store_msr(env, env->msr | (target_ulong)1 << flag); in target_cpu_copy_regs()
/qemu/target/i386/
H A Dcpu-internal.h47 } msr; member

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