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Searched refs:opc2 (Results 1 – 25 of 25) sorted by relevance

/qemu/target/ppc/translate/
H A Dvmx-ops.c.inc1 #define GEN_VR_LDX(name, opc2, opc3) \
2 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
4 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
6 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
21 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
23 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
36 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
38 #define GEN_VXFORM_207(name, opc2, opc3) \
54 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
[all …]
H A Dvsx-ops.c.inc45 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
49 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
63 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
75 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
87 #define GEN_XX3FORM_DM(name, opc2, opc3) \
105 #define GEN_VSX_XFORM_300(name, opc2, opc3, inval) \
106 GEN_HANDLER_E(name, 0x3F, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
111 #define GEN_VSX_Z23FORM_300(name, opc2, opc3, opc4, inval) \
119 GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval)
288 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
[all …]
H A Dspe-ops.c.inc6 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
85 #define GEN_SPEOP_LDST(name, opc2, sh) \
86 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
H A Dfp-ops.c.inc57 #define GEN_STXF(name, stop, opc2, opc3, type) \
58 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
H A Dvmx-impl.c.inc17 #define GEN_VR_LDX(name, opc2, opc3) \
83 #define GEN_VR_LVE(name, opc2, opc3, size) \
102 #define GEN_VR_STVE(name, opc2, opc3, size) \
230 #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
255 #define GEN_VXFORM(name, opc2, opc3) \
269 #define GEN_VXFORM_TRANS(name, opc2, opc3) \
279 #define GEN_VXFORM_ENV(name, opc2, opc3) \
1180 #define GEN_VXRFORM(name, opc2, opc3) \
1181 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
1450 #define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
[all …]
H A Dspe-impl.c.inc42 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
765 #define GEN_SPEOP_LDST(name, opc2, sh) \
H A Dfp-impl.c.inc915 #define GEN_STXF(name, stop, opc2, opc3, type) \
/qemu/target/arm/
H A Dhelper.c3557 if (ri->opc2 & 4) { in ats_access()
9666 .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, in register_cp_regs_for_features()
9678 .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, in register_cp_regs_for_features()
9697 .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, in register_cp_regs_for_features()
9709 .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, in register_cp_regs_for_features()
10081 r2->opc2 = opc2; in add_cpreg_to_hashtable()
10174 ((r->opc2 == CP_ANY) && opc2 != 0)) { in add_cpreg_to_hashtable()
10218 int crm, opc1, opc2; in define_one_arm_cp_reg_with_opaque() local
10223 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; in define_one_arm_cp_reg_with_opaque()
10224 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; in define_one_arm_cp_reg_with_opaque()
[all …]
H A Dcortex-regs.c31 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
35 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
39 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
42 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
45 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
48 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
54 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
60 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
66 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
H A Ddebug_helper.c952 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
971 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
981 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
985 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
990 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0,
999 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
1009 .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
1037 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
1075 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
1175 .opc1 = 0, .opc2 = 0, in define_debug_regs()
[all …]
H A Dsyndrome.h171 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, in syn_cp14_rt_trap() argument
177 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) in syn_cp14_rt_trap()
181 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, in syn_cp15_rt_trap() argument
187 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) in syn_cp15_rt_trap()
H A Dcpregs.h171 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ argument
173 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
864 uint8_t opc2; member
1077 uint8_t opc2, in arm_cpreg_encoding_in_idspace() argument
1091 arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2, in arm_cpreg_in_idspace()
/qemu/target/arm/tcg/
H A Dcpu64.c492 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
497 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
500 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
503 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
506 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
509 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
513 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
517 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
525 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
528 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
[all …]
H A Dcpu32.c554 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
591 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
594 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
597 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
600 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
603 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
606 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
609 .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
612 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
615 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
[all …]
H A Da32.decode50 &mcr cp opc1 crn crm opc2 rt
546 @mcr ---- .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4 &mcr
H A Dt32.decode48 &mcr !extern cp opc1 crn crm opc2 rt
708 @mcr .... .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4
H A Dneon-dp.decode445 # 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4
H A Dtranslate.c4518 int opc1, int crn, int crm, int opc2, in do_coproc_insn() argument
4521 uint32_t key = ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2); in do_coproc_insn()
4542 syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, in do_coproc_insn()
4551 syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, in do_coproc_insn()
4633 crm, opc2, s->ns ? "non-secure" : "secure"); in do_coproc_insn()
5187 do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, in trans_MCR()
5197 do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, in trans_MRC()
/qemu/hw/intc/
H A Darm_gicv3_cpuif.c562 int regno = ri->opc2 & 3; in icv_ap_read()
574 int regno = ri->opc2 & 3; in icv_ap_write()
669 trace_gicv3_icv_igrpen_read(ri->opc2 & 1 ? 1 : 0, in icv_igrpen_read()
1832 int regno = ri->opc2 & 3; in icc_ap_read()
1854 int regno = ri->opc2 & 3; in icc_ap_write()
2103 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; in icc_igrpen_read()
2124 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; in icc_igrpen_write()
2698 int regno = ri->opc2 & 3; in ich_ap_read()
2711 int regno = ri->opc2 & 3; in ich_ap_write()
2784 int regno = ri->opc2 | ((ri->crm & 1) << 3); in ich_lr_read()
[all …]
H A Darm_gicv3_kvm.c734 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
/qemu/target/ppc/
H A Dtranslate.c1356 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1359 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1362 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1365 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1368 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
1374 unsigned char opc1, opc2, opc3, opc4; member
5427 if (opc2 & 0x04) { in gen_405_mulladd_insn()
5430 if (opc2 & 0x02) { in gen_405_mulladd_insn()
6800 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
7021 if (insn->opc2 != 0xFF) { in register_insn()
[all …]
H A Dinternal.h100 EXTRACT_HELPER(opc2, 1, 5);
/qemu/hw/arm/
H A Dpxa2xx.c359 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
362 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
365 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
367 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
369 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
372 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
374 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
376 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
378 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
381 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
[all …]
H A Dpxa2xx_pic.c245 { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
/qemu/tcg/mips/
H A Dtcg-target.c.inc450 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
455 inst = (sa & 32 ? opc2 : opc1);