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Searched refs:phy (Results 1 – 23 of 23) sorted by relevance

/qemu/hw/net/
H A Detraxfs_eth.c67 if (!phy->link) { in tdk_read()
94 if (!phy->link) { in tdk_read()
140 phy->link = 1; in tdk_reset()
186 struct qemu_phy *phy; in mdio_read_req() local
189 if (phy && phy->read) { in mdio_read_req()
190 bus->data = phy->read(phy, bus->req); in mdio_read_req()
201 if (phy && phy->write) { in mdio_write_req()
202 phy->write(phy, bus->req, bus->data); in mdio_write_req()
349 struct qemu_phy phy; member
360 phy_duplex = !!(phy->read(phy, 18) & (1 << 11)); in eth_validate_duplex()
[all …]
H A Dxilinx_axienet.c154 tdk_init(struct PHY *phy) in tdk_init() argument
156 phy->regs[0] = 0x3100; in tdk_init()
162 phy->link = 1; in tdk_init()
164 phy->read = tdk_read; in tdk_init()
189 struct PHY *phy; in mdio_read_req() local
193 if (phy && phy->read) { in mdio_read_req()
194 data = phy->read(phy, reg); in mdio_read_req()
205 struct PHY *phy; in mdio_write_req() local
209 if (phy && phy->write) { in mdio_write_req()
210 phy->write(phy, reg, data); in mdio_write_req()
[all …]
H A De1000x_common.h78 e1000x_update_regs_on_link_down(uint32_t *mac, uint16_t *phy) in e1000x_update_regs_on_link_down() argument
81 phy[MII_BMSR] &= ~MII_BMSR_LINK_ST; in e1000x_update_regs_on_link_down()
82 phy[MII_BMSR] &= ~MII_BMSR_AN_COMP; in e1000x_update_regs_on_link_down()
83 phy[MII_ANLPAR] &= ~MII_ANLPAR_ACK; in e1000x_update_regs_on_link_down()
87 e1000x_update_regs_on_link_up(uint32_t *mac, uint16_t *phy) in e1000x_update_regs_on_link_up() argument
90 phy[MII_BMSR] |= MII_BMSR_LINK_ST; in e1000x_update_regs_on_link_up()
118 void e1000x_restart_autoneg(uint32_t *mac, uint16_t *phy, QEMUTimer *timer);
123 void e1000x_update_regs_on_autoneg_done(uint32_t *mac, uint16_t *phy);
H A De1000x_common.c162 void e1000x_restart_autoneg(uint32_t *mac, uint16_t *phy, QEMUTimer *timer) in e1000x_restart_autoneg() argument
164 e1000x_update_regs_on_link_down(mac, phy); in e1000x_restart_autoneg()
186 void e1000x_update_regs_on_autoneg_done(uint32_t *mac, uint16_t *phy) in e1000x_update_regs_on_autoneg_done() argument
188 e1000x_update_regs_on_link_up(mac, phy); in e1000x_update_regs_on_autoneg_done()
189 phy[MII_ANLPAR] |= MII_ANLPAR_ACK; in e1000x_update_regs_on_autoneg_done()
190 phy[MII_BMSR] |= MII_BMSR_AN_COMP; in e1000x_update_regs_on_autoneg_done()
H A Dtulip.c436 static uint16_t tulip_mii_read(TULIPState *s, int phy, int reg) in tulip_mii_read() argument
439 if (phy == 1) { in tulip_mii_read()
442 trace_tulip_mii_read(phy, reg, ret); in tulip_mii_read()
446 static void tulip_mii_write(TULIPState *s, int phy, int reg, uint16_t data) in tulip_mii_write() argument
448 trace_tulip_mii_write(phy, reg, data); in tulip_mii_write()
450 if (phy != 1) { in tulip_mii_write()
462 int op, phy, reg; in tulip_mii() local
493 phy = (s->mii_word >> 7) & 0x1f; in tulip_mii()
497 s->mii_word = tulip_mii_read(s, phy, reg); in tulip_mii()
501 phy = (s->mii_word >> 23) & 0x1f; in tulip_mii()
[all …]
H A Dimx_fec.c283 uint32_t phy = reg / 32; in imx_phy_read() local
289 if (phy != s->phy_num) { in imx_phy_read()
290 if (s->phy_consumer && phy == s->phy_consumer->phy_num) { in imx_phy_read()
293 trace_imx_phy_read_num(phy, s->phy_num); in imx_phy_read()
345 trace_imx_phy_read(val, phy, reg); in imx_phy_read()
352 uint32_t phy = reg / 32; in imx_phy_write() local
358 if (phy != s->phy_num) { in imx_phy_write()
359 if (s->phy_consumer && phy == s->phy_consumer->phy_num) { in imx_phy_write()
362 trace_imx_phy_write_num(phy, s->phy_num); in imx_phy_write()
369 trace_imx_phy_write(val, phy, reg); in imx_phy_write()
H A De1000e_core.c650 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || in e1000e_tx_pkt_send()
1740 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; in e1000e_have_autoneg()
1746 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { in e1000e_update_flowctl_status()
1765 core->phy[0][MII_BMCR] = val & ~(0x3f | in e1000e_set_phy_ctrl()
1778 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); in e1000e_set_phy_oem_bits()
1788 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; in e1000e_set_phy_page()
2279 core->phy[page][addr] = data; in e1000e_phy_reg_write()
2297 val = (val ^ data) | core->phy[page][addr]; in e1000e_set_mdic()
3315 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { in e1000e_autoneg_resume()
3461 memset(core->phy, 0, sizeof core->phy); in e1000e_reset()
[all …]
H A Digb_core.h68 uint16_t phy[MAX_PHY_REG_ADDRESS + 1]; member
H A De1000e_core.h63 uint16_t phy[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]; member
H A Dtrace-events414 tulip_mii_write(int phy, int reg, uint16_t data) "phy 0x%x reg 0x%x data 0x%04x"
415 tulip_mii_read(int phy, int reg, uint16_t data) "phy 0x%x, reg 0x%x data 0x%04x"
434 imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
435 imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
436 imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
437 imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
H A Digb_core.c558 if ((core->phy[MII_BMCR] & MII_BMCR_LOOPBACK) || in igb_tx_pkt_send()
2110 return core->phy[MII_BMCR] & MII_BMCR_AUTOEN; in igb_have_autoneg()
2126 e1000x_update_regs_on_link_down(core->mac, core->phy); in igb_link_down()
2149 e1000x_update_regs_on_link_down(core->mac, core->phy); in igb_core_set_link_status()
2152 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) { in igb_core_set_link_status()
2153 e1000x_restart_autoneg(core->mac, core->phy, in igb_core_set_link_status()
2679 core->phy[addr] = data; in igb_phy_reg_write()
2696 val = (val ^ data) | core->phy[addr]; in igb_set_mdic()
4279 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) { in igb_autoneg_resume()
4473 memset(core->phy, 0, sizeof core->phy); in igb_reset()
[all …]
H A Deepro100.c1161 uint8_t phy = (val & BITS(25, 21)) >> 21; in eepro100_read_mdi() local
1168 val, raiseint, mdi_op_name[opcode], phy, in eepro100_read_mdi()
1178 uint8_t phy = (val & BITS(25, 21)) >> 21; in eepro100_write_mdi() local
1182 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); in eepro100_write_mdi()
1183 if (phy != 1) { in eepro100_write_mdi()
1186 logout("phy must be 1 but is %u\n", phy); in eepro100_write_mdi()
1199 val, raiseint, mdi_op_name[opcode], phy, in eepro100_write_mdi()
H A Digb.c576 VMSTATE_UINT16_ARRAY(core.phy, IGBState, MAX_PHY_REG_ADDRESS + 1),
H A De1000e.c622 VMSTATE_UINT16_2DARRAY(core.phy, E1000EState,
/qemu/hw/net/fsl_etsec/
H A Dmiim.c41 uint8_t phy; in miim_read_cycle() local
45 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F; in miim_read_cycle()
46 (void)phy; /* Unreferenced */ in miim_read_cycle()
65 qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value); in miim_read_cycle()
73 uint8_t phy; in miim_write_cycle() local
77 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F; in miim_write_cycle()
78 (void)phy; /* Unreferenced */ in miim_write_cycle()
83 qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value); in miim_write_cycle()
/qemu/target/cris/
H A Dhelper.c59 target_ulong phy; in cris_cpu_tlb_fill() local
68 phy = res.phy & ~0x80000000; in cris_cpu_tlb_fill()
70 tlb_set_page(cs, address & TARGET_PAGE_MASK, phy, in cris_cpu_tlb_fill()
242 uint32_t phy = addr; in cris_cpu_get_phys_page_debug() local
253 phy = res.phy; in cris_cpu_get_phys_page_debug()
255 D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy)); in cris_cpu_get_phys_page_debug()
256 return phy; in cris_cpu_get_phys_page_debug()
H A Dmmu.c286 res->phy = tlb_pfn << TARGET_PAGE_BITS; in cris_mmu_translate_page()
336 res->phy = vaddr; in cris_mmu_translate()
347 res->phy = base | (0x0fffffff & vaddr); in cris_mmu_translate()
H A Dmmu.h11 uint32_t phy; member
/qemu/pc-bios/
H A Dpetalogix-ml605.dts147 phy-handle = < &phy7 >;
153 xlnx,phy-type = < 0x01 >;
172 phy7: phy@7 {
174 device_type = "ethernet-phy";
H A Dcanyonlands.dts389 phy-mode = "rgmii";
390 phy-map = <0x00000000>;
419 phy-mode = "rgmii";
420 phy-map = <0x00000000>;
/qemu/hw/usb/
H A Dmeson.build32 system_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c'))
/qemu/hw/scsi/
H A Dtrace-events42 …phy_handle, int dev_handle, int page) "dev %p address %d (port %d, handles: phy %d dev %d) page %d"
43 …phy_handle, int dev_handle, int page) "dev %p address %d (port %d, handles: phy %d dev %d) page %d"
/qemu/
H A DMAINTAINERS951 F: hw/usb/imx-usb-phy.c
952 F: include/hw/usb/imx-usb-phy.h