Searched refs:pll (Results 1 – 8 of 8) sorted by relevance
/qemu/hw/misc/ |
H A D | stm32l4x5_rcc.c | 207 vco_freq = muldiv64(clock_get_hz(pll->in), pll->vco_multiplier, 1); in pll_update() 210 if (!pll->channel_exists[i]) { in pll_update() 216 !pll->enabled || in pll_update() 217 !pll->channel_enabled[i] || in pll_update() 218 !pll->channel_divider[i]) { in pll_update() 324 pll_update(pll, false); in pll_set_vco_multiplier() 329 if (pll->enabled == enabled) { in pll_set_enable() 333 pll->enabled = enabled; in pll_set_enable() 334 pll_update(pll, false); in pll_set_enable() 352 pll_update(pll, false); in pll_set_channel_enable() [all …]
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H A D | bcm2835_cprman.c | 67 static bool pll_is_locked(const CprmanPllState *pll) in pll_is_locked() argument 73 static void pll_update(CprmanPllState *pll) in pll_update() argument 77 if (!pll_is_locked(pll)) { in pll_update() 78 clock_update(pll->out, 0); in pll_update() 85 clock_update(pll->out, 0); in pll_update() 92 if (pll->reg_a2w_ana[1] & pll->prediv_mask) { in pll_update() 102 freq = clock_get_hz(pll->xosc_in) * in pll_update() 107 clock_update_hz(pll->out, freq); in pll_update() 203 pll_update(pll); in pll_update_all_channels() 207 if (channel->parent == pll->id) { in pll_update_all_channels() [all …]
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H A D | npcm7xx_clk.c | 596 NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj); in npcm7xx_clk_pll_init() local 598 pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in", in npcm7xx_clk_pll_init() 599 npcm7xx_clk_update_pll_cb, pll, in npcm7xx_clk_pll_init() 601 pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out"); in npcm7xx_clk_pll_init() 637 static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll, in npcm7xx_init_clock_pll() argument 640 pll->name = init_info->name; in npcm7xx_init_clock_pll() 641 pll->clk = clk; in npcm7xx_init_clock_pll() 642 pll->reg = init_info->reg; in npcm7xx_init_clock_pll() 644 qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk), in npcm7xx_init_clock_pll()
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/qemu/hw/input/ |
H A D | tsc210x.c | 79 uint16_t pll[3]; member 178 s->pll[0] = 0x1004; in tsc210x_reset() 179 s->pll[1] = 0x0000; in tsc210x_reset() 180 s->pll[2] = 0x1fff; in tsc210x_reset() 446 return ((!s->dav) << 15) | ((s->kb.mode & 1) << 14) | s->pll[2]; in tsc2102_control_register_read() 527 return s->pll[0]; in tsc2102_audio_register_read() 530 return s->pll[1]; in tsc2102_audio_register_read() 632 s->pll[2] = value & 0x3ffff; in tsc2102_control_register_write() 742 s->pll[0] = value & 0xfffc; in tsc2102_audio_register_write() 751 s->pll[1] = value & 0xfffc; in tsc2102_audio_register_write() [all …]
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/qemu/include/hw/misc/ |
H A D | bcm2835_cprman_internals.h | 286 CprmanPllState *pll, in set_pll_init_info() argument 289 pll->id = id; in set_pll_init_info() 290 pll->reg_cm = &s->regs[PLL_INIT_INFO[id].cm_offset]; in set_pll_init_info() 291 pll->reg_a2w_ctrl = &s->regs[PLL_INIT_INFO[id].a2w_ctrl_offset]; in set_pll_init_info() 292 pll->reg_a2w_ana = &s->regs[PLL_INIT_INFO[id].a2w_ana_offset]; in set_pll_init_info() 293 pll->prediv_mask = PLL_INIT_INFO[id].prediv_mask; in set_pll_init_info() 294 pll->reg_a2w_frac = &s->regs[PLL_INIT_INFO[id].a2w_frac_offset]; in set_pll_init_info()
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H A D | stm32l4x5_rcc_internals.h | 396 static inline void set_pll_init_info(RccPllState *pll, in set_pll_init_info() argument 401 pll->id = id; in set_pll_init_info() 402 pll->vco_multiplier = 1; in set_pll_init_info() 404 pll->channel_enabled[i] = false; in set_pll_init_info() 405 pll->channel_exists[i] = PLL_INIT_INFO[id].channel_exists[i]; in set_pll_init_info() 406 pll->channel_divider[i] = PLL_INIT_INFO[id].default_channel_divider[i]; in set_pll_init_info()
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/qemu/hw/display/ |
H A D | blizzard.c | 34 int pll; member 198 s->pll = 9; in blizzard_reset() 291 return (s->pll - 1) | (1 << 7); in blizzard_reg_read() 488 s->pll = (value & 0x3f) + 1; in blizzard_reg_write()
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/qemu/tests/data/qobject/ |
H A D | qdict.txt | 4951 dvb-pll.c: 17175 4952 dvb-pll.h: 1617
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