1 #ifndef MMU_HASH32_H
2 #define MMU_HASH32_H
3
4 #ifndef CONFIG_USER_ONLY
5
6 hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash);
7 bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
8 hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
9 bool guest_visible);
10
11 /*
12 * Segment register definitions
13 */
14
15 #define SR32_T 0x80000000
16 #define SR32_KS 0x40000000
17 #define SR32_KP 0x20000000
18 #define SR32_NX 0x10000000
19 #define SR32_VSID 0x00ffffff
20
21 /*
22 * Block Address Translation (BAT) definitions
23 */
24
25 #define BATU32_BEPIU 0xf0000000
26 #define BATU32_BEPIL 0x0ffe0000
27 #define BATU32_BEPI 0xfffe0000
28 #define BATU32_BL 0x00001ffc
29 #define BATU32_VS 0x00000002
30 #define BATU32_VP 0x00000001
31
32
33 #define BATL32_BRPN 0xfffe0000
34 #define BATL32_WIMG 0x00000078
35 #define BATL32_PP 0x00000003
36
37 /*
38 * Hash page table definitions
39 */
40 #define SDR_32_HTABORG 0xFFFF0000UL
41 #define SDR_32_HTABMASK 0x000001FFUL
42
43 #define HPTES_PER_GROUP 8
44 #define HASH_PTE_SIZE_32 8
45 #define HASH_PTEG_SIZE_32 (HASH_PTE_SIZE_32 * HPTES_PER_GROUP)
46
47 #define HPTE32_V_VALID 0x80000000
48 #define HPTE32_V_VSID 0x7fffff80
49 #define HPTE32_V_SECONDARY 0x00000040
50 #define HPTE32_V_API 0x0000003f
51 #define HPTE32_V_COMPARE(x, y) (!(((x) ^ (y)) & 0x7fffffbf))
52
53 #define HPTE32_R_RPN 0xfffff000
54 #define HPTE32_R_R 0x00000100
55 #define HPTE32_R_C 0x00000080
56 #define HPTE32_R_W 0x00000040
57 #define HPTE32_R_I 0x00000020
58 #define HPTE32_R_M 0x00000010
59 #define HPTE32_R_G 0x00000008
60 #define HPTE32_R_WIMG 0x00000078
61 #define HPTE32_R_PP 0x00000003
62
ppc_hash32_hpt_base(PowerPCCPU * cpu)63 static inline hwaddr ppc_hash32_hpt_base(PowerPCCPU *cpu)
64 {
65 return cpu->env.spr[SPR_SDR1] & SDR_32_HTABORG;
66 }
67
ppc_hash32_hpt_mask(PowerPCCPU * cpu)68 static inline hwaddr ppc_hash32_hpt_mask(PowerPCCPU *cpu)
69 {
70 return ((cpu->env.spr[SPR_SDR1] & SDR_32_HTABMASK) << 16) | 0xFFFF;
71 }
72
ppc_hash32_load_hpte0(PowerPCCPU * cpu,hwaddr pte_offset)73 static inline target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu,
74 hwaddr pte_offset)
75 {
76 target_ulong base = ppc_hash32_hpt_base(cpu);
77
78 return ldl_phys(CPU(cpu)->as, base + pte_offset);
79 }
80
ppc_hash32_load_hpte1(PowerPCCPU * cpu,hwaddr pte_offset)81 static inline target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu,
82 hwaddr pte_offset)
83 {
84 target_ulong base = ppc_hash32_hpt_base(cpu);
85
86 return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2);
87 }
88
ppc_hash32_store_hpte0(PowerPCCPU * cpu,hwaddr pte_offset,target_ulong pte0)89 static inline void ppc_hash32_store_hpte0(PowerPCCPU *cpu,
90 hwaddr pte_offset, target_ulong pte0)
91 {
92 target_ulong base = ppc_hash32_hpt_base(cpu);
93
94 stl_phys(CPU(cpu)->as, base + pte_offset, pte0);
95 }
96
ppc_hash32_store_hpte1(PowerPCCPU * cpu,hwaddr pte_offset,target_ulong pte1)97 static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu,
98 hwaddr pte_offset, target_ulong pte1)
99 {
100 target_ulong base = ppc_hash32_hpt_base(cpu);
101
102 stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1);
103 }
104
ppc_hash32_pp_prot(bool key,int pp,bool nx)105 static inline int ppc_hash32_pp_prot(bool key, int pp, bool nx)
106 {
107 int prot;
108
109 if (key == 0) {
110 switch (pp) {
111 case 0x0:
112 case 0x1:
113 case 0x2:
114 prot = PAGE_READ | PAGE_WRITE;
115 break;
116
117 case 0x3:
118 prot = PAGE_READ;
119 break;
120
121 default:
122 abort();
123 }
124 } else {
125 switch (pp) {
126 case 0x0:
127 prot = 0;
128 break;
129
130 case 0x1:
131 case 0x3:
132 prot = PAGE_READ;
133 break;
134
135 case 0x2:
136 prot = PAGE_READ | PAGE_WRITE;
137 break;
138
139 default:
140 abort();
141 }
142 }
143 if (nx == 0) {
144 prot |= PAGE_EXEC;
145 }
146
147 return prot;
148 }
149
150 typedef struct {
151 uint32_t pte0, pte1;
152 } ppc_hash_pte32_t;
153
154 #endif /* CONFIG_USER_ONLY */
155
156 #endif /* MMU_HASH32_H */
157