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/qemu/tests/avocado/acpi-bits/bits-tests/
H A Dtestacpi.py259 # Find the ProcId defined by the processor object
60 processor = acpi.evaluate(cpupath)
61 # Find the UID defined by the processor object's _UID method
71 …e.test("{} Processor declaration ProcId = _MAT ProcId".format(cpupath), processor.ProcId == subtab…
73 testsuite.print_detail("Processor Declaration: {}".format(processor))
78 testsuite.print_detail("Processor Declaration: {}".format(processor))
195 …if not testsuite.test("_PSD (P-State Dependency) must exist for each processor", None not in uniqu…
217 …testsuite.test('Dependency count for each processor must be 1', unique_num_dependencies.keys() == …
218 detail(unique_num_dependencies, 'Dependency count for each processor = {} (Expected 1)')
225 …testsuite.test('_PSD.domain must be unique (thread-scoped) for each processor', len(unique_domain)…
[all …]
/qemu/hw/timer/
H A Dslavio_timer.c287 unsigned int processor = 1 << i; in slavio_timer_mem_writel() local
292 if ((val & processor) != (s->cputimer_mode & processor)) { in slavio_timer_mem_writel()
293 if (val & processor) { // counter -> user timer in slavio_timer_mem_writel()
306 s->cputimer_mode |= processor; in slavio_timer_mem_writel()
313 s->cputimer_mode &= ~processor; in slavio_timer_mem_writel()
H A Dtrace-events9 slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer se…
11 slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started"
12 slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped"
13 slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to u…
14 slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user time…
/qemu/docs/specs/
H A Dfsi.rst13 FSI allows a service processor access to the internal buses of a host POWER
14 processor to perform configuration or debugging. FSI has long existed in POWER
18 Working backwards from the POWER processor, the fundamental pieces of interest
32 3. The FSI master: A controller in the platform service processor (e.g. BMC)
H A Dppc-xive.rst5 The POWER9 processor comes with a new interrupt controller
26 the chip/processor. They are configured to feed the IVRE with
118 the processor HW threads. It maintains the interrupt context state of
H A Dsev-guest-firmware.rst74 | 0xffffffe0 | 8 | Application processor entry point code |
H A Dppc-spapr-xive.rst4 The POWER9 processor comes with a new interrupt controller
/qemu/target/ppc/translate/
H A Dprocessor-ctrl-impl.c.inc28 * Before Power ISA 2.07, processor control instructions were only
52 * Before Power ISA 2.07, processor control instructions were only
H A Dmisc-impl.c.inc132 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
/qemu/docs/system/riscv/
H A Dshakti-c.rst7 Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
8 is a 64bit RV64GCSUN processor core.
/qemu/docs/system/arm/
H A Demcraft-sf2.rst7 The SoC is based on a Cortex-M4 processor.
/qemu/target/loongarch/
H A DREADME3 LoongArch is the general processor architecture of Loongson.
/qemu/docs/system/i386/
H A Damd-memory-encryption.rst14 Key management for this feature is handled by a separate processor known as the
15 AMD secure processor (AMD-SP), which is present in AMD SOCs. Firmware running
258 …<https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.…
268 <https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.p…
H A Dhyperv.rst57 processor index information. This enlightenment makes sense in conjunction with
64 virtual processor run time in 100ns units. This gives guest operating system an
H A Dxen.rst144 accelerated Xen PV timers and inter-processor interrupts (IPIs).
/qemu/docs/devel/
H A Datomics.rst67 and the operations of each individual processor appear in this sequence
140 stores: both the compiler and the processor are free to reorder
203 the processor will guarantee that the first LOAD will appear to happen
216 needs a processor barrier. On strongly-ordered architectures such
480 because the read of ``y`` can be moved (by either the processor or the
H A Dlockcnt.txt101 processor and the compiler see all required memory barriers.
255 list during the walk. QLIST_FOREACH_RCU ensures that the processor and
/qemu/docs/system/
H A Dcpu-models-x86.rst.inc76 or 7 only. (The Cascade Lake Xeon processor with *stepping 5 is
205 processor is vulnerable, use the Intel VERW instruction (a
206 processor-level instruction that performs checks on memory access) as
359 Common KVM processor (32 & 64 bit variants).
/qemu/docs/spin/
H A Dtcg-exclusive.promela16 * Tunable processor macros: N_CPUS, N_EXCLUSIVE, N_CYCLES, USE_MUTEX,
/qemu/docs/system/ppc/
H A Dpseries.rst17 * Multi processor support for many Power processors generations: POWER7,
171 on hypervisor mode on a Power processor (this function was restricted to
H A Dpowernv.rst18 * Multi processor support for POWER8, POWER8NVL and POWER9.
/qemu/docs/interop/
H A Dvhost-user.json31 # @rpmsg: virtio remote processor messaging
/qemu/target/arm/tcg/
H A Dt16.decode205 # Change processor state
/qemu/target/hexagon/
H A DREADME2 processor(DSP). We also support Hexagon Vector eXtensions (HVX). HVX
253 structure, and update the visible processor state when we commit the packet.
/qemu/qapi/
H A Dmisc-target.json434 # @ipi: The post is an inter-processor interrupt (IPI).

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