/qemu/tests/avocado/acpi-bits/bits-tests/ |
H A D | testacpi.py2 | 59 # Find the ProcId defined by the processor object 60 processor = acpi.evaluate(cpupath) 61 # Find the UID defined by the processor object's _UID method 71 …e.test("{} Processor declaration ProcId = _MAT ProcId".format(cpupath), processor.ProcId == subtab… 73 testsuite.print_detail("Processor Declaration: {}".format(processor)) 78 testsuite.print_detail("Processor Declaration: {}".format(processor)) 195 …if not testsuite.test("_PSD (P-State Dependency) must exist for each processor", None not in uniqu… 217 …testsuite.test('Dependency count for each processor must be 1', unique_num_dependencies.keys() == … 218 detail(unique_num_dependencies, 'Dependency count for each processor = {} (Expected 1)') 225 …testsuite.test('_PSD.domain must be unique (thread-scoped) for each processor', len(unique_domain)… [all …]
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/qemu/hw/timer/ |
H A D | slavio_timer.c | 287 unsigned int processor = 1 << i; in slavio_timer_mem_writel() local 292 if ((val & processor) != (s->cputimer_mode & processor)) { in slavio_timer_mem_writel() 293 if (val & processor) { // counter -> user timer in slavio_timer_mem_writel() 306 s->cputimer_mode |= processor; in slavio_timer_mem_writel() 313 s->cputimer_mode &= ~processor; in slavio_timer_mem_writel()
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H A D | trace-events | 9 slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer se… 11 slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started" 12 slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped" 13 slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to u… 14 slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user time…
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/qemu/docs/specs/ |
H A D | fsi.rst | 13 FSI allows a service processor access to the internal buses of a host POWER 14 processor to perform configuration or debugging. FSI has long existed in POWER 18 Working backwards from the POWER processor, the fundamental pieces of interest 32 3. The FSI master: A controller in the platform service processor (e.g. BMC)
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H A D | ppc-xive.rst | 5 The POWER9 processor comes with a new interrupt controller 26 the chip/processor. They are configured to feed the IVRE with 118 the processor HW threads. It maintains the interrupt context state of
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H A D | sev-guest-firmware.rst | 74 | 0xffffffe0 | 8 | Application processor entry point code |
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H A D | ppc-spapr-xive.rst | 4 The POWER9 processor comes with a new interrupt controller
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/qemu/target/ppc/translate/ |
H A D | processor-ctrl-impl.c.inc | 28 * Before Power ISA 2.07, processor control instructions were only 52 * Before Power ISA 2.07, processor control instructions were only
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H A D | misc-impl.c.inc | 132 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
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/qemu/docs/system/riscv/ |
H A D | shakti-c.rst | 7 Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C 8 is a 64bit RV64GCSUN processor core.
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/qemu/docs/system/arm/ |
H A D | emcraft-sf2.rst | 7 The SoC is based on a Cortex-M4 processor.
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/qemu/target/loongarch/ |
H A D | README | 3 LoongArch is the general processor architecture of Loongson.
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/qemu/docs/system/i386/ |
H A D | amd-memory-encryption.rst | 14 Key management for this feature is handled by a separate processor known as the 15 AMD secure processor (AMD-SP), which is present in AMD SOCs. Firmware running 258 …<https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.… 268 <https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.p…
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H A D | hyperv.rst | 57 processor index information. This enlightenment makes sense in conjunction with 64 virtual processor run time in 100ns units. This gives guest operating system an
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H A D | xen.rst | 144 accelerated Xen PV timers and inter-processor interrupts (IPIs).
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/qemu/docs/devel/ |
H A D | atomics.rst | 67 and the operations of each individual processor appear in this sequence 140 stores: both the compiler and the processor are free to reorder 203 the processor will guarantee that the first LOAD will appear to happen 216 needs a processor barrier. On strongly-ordered architectures such 480 because the read of ``y`` can be moved (by either the processor or the
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H A D | lockcnt.txt | 101 processor and the compiler see all required memory barriers. 255 list during the walk. QLIST_FOREACH_RCU ensures that the processor and
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/qemu/docs/system/ |
H A D | cpu-models-x86.rst.inc | 76 or 7 only. (The Cascade Lake Xeon processor with *stepping 5 is 205 processor is vulnerable, use the Intel VERW instruction (a 206 processor-level instruction that performs checks on memory access) as 359 Common KVM processor (32 & 64 bit variants).
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/qemu/docs/spin/ |
H A D | tcg-exclusive.promela | 16 * Tunable processor macros: N_CPUS, N_EXCLUSIVE, N_CYCLES, USE_MUTEX,
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/qemu/docs/system/ppc/ |
H A D | pseries.rst | 17 * Multi processor support for many Power processors generations: POWER7, 171 on hypervisor mode on a Power processor (this function was restricted to
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H A D | powernv.rst | 18 * Multi processor support for POWER8, POWER8NVL and POWER9.
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/qemu/docs/interop/ |
H A D | vhost-user.json | 31 # @rpmsg: virtio remote processor messaging
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/qemu/target/arm/tcg/ |
H A D | t16.decode | 205 # Change processor state
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/qemu/target/hexagon/ |
H A D | README | 2 processor(DSP). We also support Hexagon Vector eXtensions (HVX). HVX 253 structure, and update the visible processor state when we commit the packet.
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/qemu/qapi/ |
H A D | misc-target.json | 434 # @ipi: The post is an inter-processor interrupt (IPI).
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