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Searched refs:qdev_prop_set_uint32 (Results 1 – 25 of 105) sorted by relevance

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/qemu/hw/isa/
H A Disa-superio.c58 qdev_prop_set_uint32(d, "index", i); in isa_superio_realize()
60 qdev_prop_set_uint32(d, "iobase", in isa_superio_realize()
64 qdev_prop_set_uint32(d, "irq", k->parallel.get_irq(sio, i)); in isa_superio_realize()
97 qdev_prop_set_uint32(d, "index", i); in isa_superio_realize()
99 qdev_prop_set_uint32(d, "iobase", in isa_superio_realize()
103 qdev_prop_set_uint32(d, "irq", k->serial.get_irq(sio, i)); in isa_superio_realize()
125 qdev_prop_set_uint32(d, "iobase", k->floppy.get_iobase(sio, 0)); in isa_superio_realize()
128 qdev_prop_set_uint32(d, "irq", k->floppy.get_irq(sio, 0)); in isa_superio_realize()
156 qdev_prop_set_uint32(d, "iobase", k->ide.get_iobase(sio, 0)); in isa_superio_realize()
159 qdev_prop_set_uint32(d, "iobase2", k->ide.get_iobase(sio, 1)); in isa_superio_realize()
[all …]
/qemu/hw/cpu/
H A Darm11mpcore.c80 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); in mpcore_priv_realize()
85 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); in mpcore_priv_realize()
86 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); in mpcore_priv_realize()
87 qdev_prop_set_uint32(gicdev, "num-priority-bits", in mpcore_priv_realize()
101 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); in mpcore_priv_realize()
106 qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); in mpcore_priv_realize()
127 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); in mpcore_priv_initfn()
H A Da9mpcore.c69 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); in a9mp_priv_realize()
76 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); in a9mp_priv_realize()
77 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); in a9mp_priv_realize()
78 qdev_prop_set_uint32(gicdev, "num-priority-bits", in a9mp_priv_realize()
100 qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); in a9mp_priv_realize()
107 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); in a9mp_priv_realize()
114 qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); in a9mp_priv_realize()
H A Da15mpcore.c47 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); in a15mp_priv_initfn()
62 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); in a15mp_priv_realize()
63 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); in a15mp_priv_realize()
/qemu/hw/microblaze/
H A Dpetalogix_s3adsp1800_mmu.c93 qdev_prop_set_uint32(dev, "kind-of-intr", in petalogix_s3adsp1800_init()
111 qdev_prop_set_uint32(dev, "one-timer-only", 0); in petalogix_s3adsp1800_init()
112 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); in petalogix_s3adsp1800_init()
119 qdev_prop_set_uint32(dev, "tx-ping-pong", 0); in petalogix_s3adsp1800_init()
120 qdev_prop_set_uint32(dev, "rx-ping-pong", 0); in petalogix_s3adsp1800_init()
H A Dpetalogix_ml605_mmu.c114 qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); in petalogix_ml605_init()
129 qdev_prop_set_uint32(dev, "one-timer-only", 0); in petalogix_ml605_init()
130 qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); in petalogix_ml605_init()
148 qdev_prop_set_uint32(eth0, "rxmem", 0x1000); in petalogix_ml605_init()
149 qdev_prop_set_uint32(eth0, "txmem", 0x1000); in petalogix_ml605_init()
162 qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000); in petalogix_ml605_init()
/qemu/hw/misc/macio/
H A Dmacio.c105 qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0); in macio_common_realize()
106 qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK); in macio_common_realize()
107 qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4); in macio_common_realize()
108 qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial); in macio_common_realize()
109 qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial); in macio_common_realize()
126 qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid); in macio_realize_ide()
202 qdev_prop_set_uint32(DEVICE(ide), "addr", addr); in macio_init_ide()
220 qdev_prop_set_uint32(dev, "size", MACIO_NVRAM_SIZE); in macio_oldworld_init()
221 qdev_prop_set_uint32(dev, "it_shift", 4); in macio_oldworld_init()
275 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); in macio_newworld_realize()
/qemu/hw/riscv/
H A Dopentitan.c178 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); in lowrisc_ibex_soc_realize()
179 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); in lowrisc_ibex_soc_realize()
180 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); in lowrisc_ibex_soc_realize()
181 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); in lowrisc_ibex_soc_realize()
182 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32); in lowrisc_ibex_soc_realize()
183 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); in lowrisc_ibex_soc_realize()
184 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); in lowrisc_ibex_soc_realize()
185 qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size); in lowrisc_ibex_soc_realize()
/qemu/hw/intc/
H A Dsifive_plic.c485 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); in type_init()
486 qdev_prop_set_uint32(dev, "num-sources", num_sources); in type_init()
487 qdev_prop_set_uint32(dev, "num-priorities", num_priorities); in type_init()
488 qdev_prop_set_uint32(dev, "priority-base", priority_base); in type_init()
489 qdev_prop_set_uint32(dev, "pending-base", pending_base); in type_init()
490 qdev_prop_set_uint32(dev, "enable-base", enable_base); in type_init()
491 qdev_prop_set_uint32(dev, "enable-stride", enable_stride); in type_init()
492 qdev_prop_set_uint32(dev, "context-base", context_base); in type_init()
493 qdev_prop_set_uint32(dev, "context-stride", context_stride); in type_init()
494 qdev_prop_set_uint32(dev, "aperture-size", aperture_size); in type_init()
H A Driscv_aclint.c366 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); in riscv_aclint_mtimer_create()
367 qdev_prop_set_uint32(dev, "num-harts", num_harts); in riscv_aclint_mtimer_create()
368 qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); in riscv_aclint_mtimer_create()
369 qdev_prop_set_uint32(dev, "time-base", time_base); in riscv_aclint_mtimer_create()
370 qdev_prop_set_uint32(dev, "aperture-size", size); in riscv_aclint_mtimer_create()
371 qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); in riscv_aclint_mtimer_create()
542 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); in riscv_aclint_swi_create()
543 qdev_prop_set_uint32(dev, "num-harts", num_harts); in riscv_aclint_swi_create()
544 qdev_prop_set_uint32(dev, "sswi", sswi ? true : false); in riscv_aclint_swi_create()
H A Drealview_gic.c35 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", numirq); in realview_gic_realize()
63 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", 1); in realview_gic_init()
/qemu/hw/arm/
H A Dmps3r.c270 qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus); in create_gic()
271 qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL); in create_gic()
341 qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ); in create_uart()
421 qdev_prop_set_uint32(orgate, "num-lines", 2); in mps3r_common_init()
439 qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines", in mps3r_common_init()
516 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0); in mps3r_common_init()
517 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2); in mps3r_common_init()
518 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008); in mps3r_common_init()
519 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360); in mps3r_common_init()
532 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]); in mps3r_common_init()
[all …]
H A Dmps2.c228 qdev_prop_set_uint32(armv7m, "num-irq", 32); in mps2_common_init()
231 qdev_prop_set_uint32(armv7m, "num-irq", 64); in mps2_common_init()
300 qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); in mps2_common_init()
344 qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); in mps2_common_init()
397 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); in mps2_common_init()
398 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); in mps2_common_init()
399 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); in mps2_common_init()
411 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000); in mps2_common_init()
H A Dmsf2-soc.c136 qdev_prop_set_uint32(armv7m, "num-irq", 81); in m2sxxx_soc_realize()
161 qdev_prop_set_uint32(dev, "clock-frequency", in m2sxxx_soc_realize()
174 qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); in m2sxxx_soc_realize()
175 qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); in m2sxxx_soc_realize()
H A Drealview.c64 qdev_prop_set_uint32(splitter, "num-lines", 2); in split_irq_from_named()
182 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); in realview_init()
183 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); in realview_init()
189 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); in realview_init()
209 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); in realview_init()
H A Dstm32l4x5_soc.c201 qdev_prop_set_uint32(armv7m, "num-irq", 96); in stm32l4x5_soc_realize()
202 qdev_prop_set_uint32(armv7m, "num-prio-bits", 4); in stm32l4x5_soc_realize()
220 qdev_prop_set_uint32(dev, "mode-reset", in stm32l4x5_soc_realize()
222 qdev_prop_set_uint32(dev, "ospeed-reset", in stm32l4x5_soc_realize()
224 qdev_prop_set_uint32(dev, "pupd-reset", in stm32l4x5_soc_realize()
H A Dmsf2-som.c76 qdev_prop_set_uint32(dev, "apb0div", 2); in emcraft_sf2_s2s010_init()
77 qdev_prop_set_uint32(dev, "apb1div", 2); in emcraft_sf2_s2s010_init()
H A Dhighbank.c262 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); in calxeda_init()
263 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); in calxeda_init()
279 qdev_prop_set_uint32(dev, "freq0", 150000000); in calxeda_init()
280 qdev_prop_set_uint32(dev, "freq1", 150000000); in calxeda_init()
H A Dmps2-tz.c447 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); in make_uart()
470 qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); in make_scc()
471 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); in make_scc()
472 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); in make_scc()
473 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); in make_scc()
493 qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); in make_fpgaio()
830 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); in mps2tz_common_init()
831 qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); in mps2tz_common_init()
833 qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns); in mps2tz_common_init()
836 qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s); in mps2tz_common_init()
[all …]
/qemu/hw/ppc/
H A Dprep.c269 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); in ibm_40p_init()
291 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); in ibm_40p_init()
311 qdev_prop_set_uint32(dev, "iobase", 0x830); in ibm_40p_init()
312 qdev_prop_set_uint32(dev, "irq", 10); in ibm_40p_init()
321 qdev_prop_set_uint32(dev, "config", 12); in ibm_40p_init()
326 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); in ibm_40p_init()
327 qdev_prop_set_uint32(dev, "equipment", 0xc0); in ibm_40p_init()
346 qdev_prop_set_uint32(dev, "data_width", 1); in ibm_40p_init()
/qemu/hw/ide/
H A Disa.c89 qdev_prop_set_uint32(dev, "iobase", iobase); in isa_ide_init()
90 qdev_prop_set_uint32(dev, "iobase2", iobase2); in isa_ide_init()
91 qdev_prop_set_uint32(dev, "irq", irqnum); in isa_ide_init()
/qemu/include/hw/net/
H A Dne2000-isa.h29 qdev_prop_set_uint32(dev, "iobase", base); in isa_ne2000_init()
30 qdev_prop_set_uint32(dev, "irq", irq); in isa_ne2000_init()
/qemu/hw/m68k/
H A Dq800.c430 qdev_prop_set_uint32(dev, "disabled", 0); in q800_machine_init()
431 qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK); in q800_machine_init()
432 qdev_prop_set_uint32(dev, "it_shift", 1); in q800_machine_init()
436 qdev_prop_set_uint32(dev, "chnBtype", 0); in q800_machine_init()
437 qdev_prop_set_uint32(dev, "chnAtype", 0); in q800_machine_init()
528 qdev_prop_set_uint32(DEVICE(&m->mac_nubus_bridge), "slot-available-mask", in q800_machine_init()
563 qdev_prop_set_uint32(dev, "slot", 9); in q800_machine_init()
564 qdev_prop_set_uint32(dev, "width", graphic_width); in q800_machine_init()
565 qdev_prop_set_uint32(dev, "height", graphic_height); in q800_machine_init()
/qemu/hw/sparc/
H A Dsun4m.c291 qdev_prop_set_uint32(dev, "version", version); in iommu_init()
385 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); in slavio_timer_init_all()
460 qdev_prop_set_uint32(dev, "version", version); in ecc_init()
490 qdev_prop_set_uint32(dev, "vram_size", vram_size); in tcx_init()
542 qdev_prop_set_uint32(dev, "vram-size", vram_size); in cg3_init()
972 qdev_prop_set_uint32(dev, "it_shift", 1); in sun4m_hw_init()
975 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); in sun4m_hw_init()
976 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); in sun4m_hw_init()
990 qdev_prop_set_uint32(dev, "disabled", 0); in sun4m_hw_init()
992 qdev_prop_set_uint32(dev, "it_shift", 1); in sun4m_hw_init()
[all …]
/qemu/include/hw/timer/
H A Di8254.h56 qdev_prop_set_uint32(dev, "iobase", base); in OBJECT_DECLARE_TYPE()
72 qdev_prop_set_uint32(dev, "iobase", base); in kvm_pit_init()

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