/qemu/tests/qtest/ |
H A D | sifive-e-aon-watchdog-test.c | 68 tmp = qtest_readl(qts, WDOG_BASE + WDOGCOUNT); in test_wdogcount() 135 tmp = qtest_readl(qts, WDOG_BASE + WDOGCMP0); in test_wdogcmp0() 217 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_watchdog() 230 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_watchdog() 243 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_watchdog() 259 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_scaled_watchdog() 272 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_scaled_watchdog() 285 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_scaled_watchdog() 301 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_periodic_int() 313 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_periodic_int() [all …]
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H A D | microbit-test.c | 33 if (qtest_readl(qts, event_addr) == 1) { in uart_wait_for_event() 58 out[i] = qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD); in uart_rw_to_rxd() 123 val = qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_EVENT_TXDSENT); in i2c_read_byte() 128 val = qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_EVENT_RXDREADY); in i2c_read_byte() 130 val = qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_REG_RXD); in i2c_read_byte() 181 g_assert_cmpuint(qtest_readl(qts, base + i * 4), ==, i); in fill_and_erase() 193 value = qtest_readl(qts, NRF51_NVMC_BASE + NRF51_NVMC_READY); in test_nrf51_nvmc() 233 g_assert_cmpuint(qtest_readl(qts, NRF51_FLASH_BASE + i * 4), in test_nrf51_nvmc() 243 g_assert_cmpuint(qtest_readl(qts, NRF51_UICR_BASE + i * 4), in test_nrf51_nvmc() 259 g_assert_cmpuint(qtest_readl(qts, NRF51_UICR_BASE + i * 4), in test_nrf51_nvmc() [all …]
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H A D | aspeed_hace-test.c | 170 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_md5() 182 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_md5() 203 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha256() 215 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha256() 236 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha512() 248 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha512() 280 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha256_sg() 299 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha256_sg() 331 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha512_sg() 350 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha512_sg() [all …]
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H A D | xlnx-can-test.c | 153 status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); in test_can_bus() 156 status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); in test_can_bus() 189 status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); in test_can_loopback() 203 status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); in test_can_loopback() 238 status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); in test_can_filter() 241 status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); in test_can_filter() 288 status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); in test_can_sleepmode() 291 status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); in test_can_sleepmode() 301 status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); in test_can_sleepmode() 334 status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); in test_can_snoopmode() [all …]
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H A D | xlnx-canfd-test.c | 153 status = qtest_readl(qts, CANFD0_BASE_ADDR + R_SR_OFFSET); in configure_canfd() 157 status = qtest_readl(qts, CANFD1_BASE_ADDR + R_SR_OFFSET); in configure_canfd() 197 fifo_status_reg_value = qtest_readl(qts, can_base_addr + in read_data() 207 buf_rx[0] = qtest_readl(qts, can_base_addr + R_RX0_ID_OFFSET); in read_data() 211 buf_rx[i + 2] = qtest_readl(qts, in read_data() 299 status = qtest_readl(qts, CANFD0_BASE_ADDR + R_SR_OFFSET); in test_can_data_transfer() 303 status = qtest_readl(qts, CANFD1_BASE_ADDR + R_SR_OFFSET); in test_can_data_transfer() 339 status = qtest_readl(qts, CANFD0_BASE_ADDR + R_SR_OFFSET); in test_canfd_data_transfer() 343 status = qtest_readl(qts, CANFD1_BASE_ADDR + R_SR_OFFSET); in test_canfd_data_transfer() 378 status = qtest_readl(qts, CANFD0_BASE_ADDR + R_SR_OFFSET); in test_can_loopback() [all …]
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H A D | stm32l4x5_usart-test.c | 55 return qtest_readl(qts, NVIC_ISPR1) & (1 << n); in check_nvic_pending() 76 if ((qtest_readl(qts, event_addr) & flag)) { in usart_wait_for_flag() 94 out[i] = qtest_readl(qts, USART1_BASE_ADDR + A_RDR); in usart_receive_string() 135 value = qtest_readl(qts, (RCC_BASE_ADDR + A_CR)); in init_clocks() 145 value = qtest_readl(qts, (RCC_BASE_ADDR + A_CFGR)); in init_clocks() 188 cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); in init_uart() 203 const uint32_t tdr = qtest_readl(qts, USART1_BASE_ADDR + A_TDR); in test_write_read() 218 g_assert_cmphex(qtest_readl(qts, USART1_BASE_ADDR + A_RDR), ==, 'a'); in test_receive_char() 222 cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); in test_receive_char() 227 g_assert_cmphex(qtest_readl(qts, USART1_BASE_ADDR + A_RDR), ==, 'b'); in test_receive_char() [all …]
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H A D | aspeed_gpio-test.c | 67 value = qtest_readl(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE); in test_set_input_pins() 71 value = qtest_readl(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE); in test_set_input_pins()
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H A D | tpm-util.c | 38 start = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); in tpm_util_crb_transfer() 46 start = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); in tpm_util_crb_transfer() 48 sts = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); in tpm_util_crb_transfer()
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H A D | npcm7xx_pwm-test.c | 291 uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL); in read_pclk() 293 uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1); in read_pclk() 294 uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2); in read_pclk() 299 pllcon = qtest_readl(qts, CLK_BA + PLLCON0); in read_pclk() 303 pllcon = qtest_readl(qts, CLK_BA + PLLCON1); in read_pclk() 365 return qtest_readl(qts, td->module->base_addr + offset); in pwm_read()
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H A D | qtest_aspeed.c | 27 v = qtest_readl(s, baseaddr + A_I2CC_FUN_CTRL) | A_I2CD_MASTER_EN; in aspeed_i2c_startup() 54 v = qtest_readl(s, baseaddr + A_I2CD_BYTE_BUF) >> 8; in aspeed_i2c_read_n()
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H A D | fuzz-xlnx-dp-test.c | 18 qtest_readl(s, 0xfd4a03ac); in test_fuzz_xlnx_dp_0x3ac()
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H A D | tpm-tis-util.c | 465 sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS)); in tpm_tis_transfer() 479 sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS)); in tpm_tis_transfer() 485 sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS)); in tpm_tis_transfer()
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H A D | prom-env-test.c | 36 signature = qtest_readl(qts, ADDRESS); in check_guest_memory()
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H A D | libqtest-single.h | 252 return qtest_readl(global_qtest, addr); in readl()
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H A D | npcm7xx_adc-test.c | 100 return qtest_readl(qts, adc->base_addr + CON_OFFSET); in adc_read_con() 110 return qtest_readl(qts, adc->base_addr + DATA_OFFSET); in adc_read_data()
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H A D | npcm7xx_sdhci-test.c | 139 g_assert_cmphex(qtest_readl(qts, addr) | mask, ==, in test_reset()
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H A D | npcm_gmac-test.c | 174 return qtest_readl(qts, mod->base_addr + regno); in gmac_read()
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H A D | aspeed_fsi-test.c | 46 return qtest_readl(s, aspeed_fsi_base_addr + reg); in aspeed_fsi_readl()
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/qemu/tests/qtest/libqos/ |
H A D | virtio-mmio.c | 34 return qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off); in qvirtio_mmio_config_readl() 50 lo = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES); in qvirtio_mmio_get_features() 54 hi = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES); in qvirtio_mmio_get_features() 83 return (uint8_t)qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_STATUS); in qvirtio_mmio_get_status() 97 isr = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 1; in qvirtio_mmio_get_queue_isr_status() 111 isr = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 2; in qvirtio_mmio_get_config_isr_status() 137 g_assert_cmphex(qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_PFN), ==, 0); in qvirtio_mmio_queue_select() 143 return (uint16_t)qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NUM_MAX); in qvirtio_mmio_get_queue_size() 242 magic = qtest_readl(qts, addr + QVIRTIO_MMIO_MAGIC_VALUE); in qvirtio_mmio_init_device() 245 dev->version = qtest_readl(qts, addr + QVIRTIO_MMIO_VERSION); in qvirtio_mmio_init_device() [all …]
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H A D | sdhci-cmd.c | 32 msg_frag = qtest_readl(qts, reg); in read_fifo()
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H A D | rtas.c | 26 ret[i] = qtest_readl(qts, target_ret + i * sizeof(uint32_t)); in qrtas_copy_ret()
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H A D | virtio-pci.c | 134 data = qtest_readl(dev->pdev->bus->qts, vqpci->msix_addr); in qvirtio_pci_get_queue_isr_status() 158 data = qtest_readl(dev->pdev->bus->qts, dev->config_msix_addr); in qvirtio_pci_get_config_isr_status()
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H A D | generic-pcihost.c | 74 return qtest_readl(bus->qts, s->gpex_pio_base + addr); in qpci_generic_pio_readl()
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/qemu/tests/qtest/fuzz/ |
H A D | meson.build | 25 '-Wl,-wrap,qtest_readl',
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H A D | qtest_wrappers.c | 34 WRAP(uint32_t , qtest_readl(QTestState *s, uint64_t addr)) in WRAP()
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