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Searched refs:rcr (Results 1 – 7 of 7) sorted by relevance

/qemu/hw/net/
H A Dsmc91c111.c36 uint16_t rcr; member
67 VMSTATE_UINT16(rcr, smc91c111_state),
137 if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) { in smc91c111_can_receive()
300 s->rcr = 0; in smc91c111_reset()
335 SET_LOW(rcr, value); in smc91c111_writeb()
338 SET_HIGH(rcr, value); in smc91c111_writeb()
339 if (s->rcr & RCR_SOFT_RST) { in smc91c111_writeb()
519 return s->rcr & 0xff; in smc91c111_readb()
521 return s->rcr >> 8; in smc91c111_readb()
688 if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) in smc91c111_receive()
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H A Dmcf_fec.c51 uint32_t rcr; member
310 s->rcr = 0x05ee0001; in mcf_fec_reset()
374 case 0x084: return s->rcr; in mcf_fec_read()
444 s->rcr = value & 0x07ff003f; in mcf_fec_write()
580 if (size > (s->rcr >> 16)) { in mcf_fec_receive()
/qemu/hw/isa/
H A Dpiix.c172 d->rcr = 0; in piix_reset()
202 s->rcr = 0; in piix4_post_load()
225 return (piix3->rcr != 0); in piix3_rcr_needed()
234 VMSTATE_UINT8(rcr, PIIXState),
264 VMSTATE_UINT8_V(rcr, PIIXState, 3),
277 d->rcr = val & 2; /* keep System Reset type only */ in rcr_write()
284 return d->rcr; in rcr_read()
/qemu/include/hw/southbridge/
H A Dpiix.h66 uint8_t rcr; member
/qemu/hw/misc/
H A Dnpcm7xx_clk.c846 uint32_t rcr; in npcm7xx_clk_perform_watchdog_reset() local
849 rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n]; in npcm7xx_clk_perform_watchdog_reset()
850 if (rcr & NPCM7XX_CLK_WDRCR_CA9C) { in npcm7xx_clk_perform_watchdog_reset()
855 __func__, rcr); in npcm7xx_clk_perform_watchdog_reset()
/qemu/hw/arm/
H A Domap1.c2971 uint16_t rcr[2]; member
3042 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; in omap_mcbsp_source_tick()
3183 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ in omap_mcbsp_read()
3213 return s->rcr[1]; in omap_mcbsp_read()
3215 return s->rcr[0]; in omap_mcbsp_read()
3319 s->rcr[1] = value & 0xffff; in omap_mcbsp_writeh()
3322 s->rcr[0] = value & 0x7fe0; in omap_mcbsp_writeh()
3459 memset(&s->rcr, 0, sizeof(s->rcr)); in omap_mcbsp_reset()
/qemu/tests/tcg/i386/
H A Dtest-i386.c146 #define OP rcr