| /qemu/tests/tcg/loongarch64/ |
| H A D | test_pcadd.c | 8 uint64_t rd1 = 0; \
14 : "=r"(rd1), "=r"(rd2) \
16 rm = rd2 - rd1; \
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| /qemu/target/arm/tcg/ |
| H A D | translate.c | 1484 int rdhi, rdlo, rd0, rd1, i; in disas_iwmmxt_insn() local
1668 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1690 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1712 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1726 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1745 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1761 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1783 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1803 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
2006 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
[all …]
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| H A D | translate-neon.c | 1683 TCGv_i32 rd0, rd1; in DO_PREWIDEN() local
1711 rd1 = tcg_temp_new_i32(); in DO_PREWIDEN()
1725 narrowfn(rd1, rn_64); in DO_PREWIDEN()
1728 write_neon_element32(rd1, a->vd, 1, MO_32); in DO_PREWIDEN()
1772 TCGv_i64 rd0, rd1, tmp; in DO_NARROW_3D() local
1799 rd1 = tcg_temp_new_i64(); in DO_NARROW_3D()
1809 opfn(rd1, rn, rm); in DO_NARROW_3D()
1817 accfn(rd1, tmp, rd1); in DO_NARROW_3D()
2937 TCGv_i32 rd0, rd1; in do_vmovn() local
2963 rd1 = tcg_temp_new_i32(); in do_vmovn()
[all …]
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| /qemu/tests/tcg/mips/user/isa/r5900/ |
| H A D | test_r5900_multu.c | 50 uint64_t rd1 = multu1(rs, rt); in multu_variants() local
52 assert(rd == rd1); in multu_variants()
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| H A D | test_r5900_maddu.c | 58 int64_t rd1 = maddu1(a, rs, rt); in maddu_variants() local
60 assert(rd == rd1); in maddu_variants()
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| H A D | test_r5900_mult.c | 50 int64_t rd1 = mult1(rs, rt); in mult_variants() local
52 assert(rd == rd1); in mult_variants()
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| H A D | test_r5900_madd.c | 58 int64_t rd1 = madd1(a, rs, rt); in madd_variants() local
60 assert(rd == rd1); in madd_variants()
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| /qemu/target/riscv/ |
| H A D | xthead.decode | 14 %rd1 7:5
30 &th_pair rd1 rs rd2 sh2
42 @th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2
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| /qemu/hw/intc/ |
| H A D | arm_gicv3_its.c | 852 uint64_t rd1, rd2; in process_movall() local
854 rd1 = FIELD_EX64(cmdpkt[2], MOVALL_2, RDBASE1); in process_movall()
857 trace_gicv3_its_cmd_movall(rd1, rd2); in process_movall()
859 if (rd1 >= s->gicv3->num_cpu) { in process_movall()
863 __func__, rd1, s->gicv3->num_cpu); in process_movall()
874 if (rd1 == rd2) { in process_movall()
880 gicv3_redist_movall_lpis(&s->gicv3->cpu[rd1], &s->gicv3->cpu[rd2]); in process_movall()
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| H A D | trace-events | 193 gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " R…
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| /qemu/target/riscv/insn_trans/ |
| H A D | trans_xthead.c.inc | 910 if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
925 gen_set_gpr(ctx, a->rd1, t1);
952 TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
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| /qemu/tcg/arm/ |
| H A D | tcg-target.c.inc | 920 TCGReg rd1, TCGReg rn, TCGReg rm)
924 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
928 TCGReg rd1, TCGReg rn, TCGReg rm)
932 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
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| /qemu/disas/ |
| H A D | nanomips.c | 10021 const char *rd1 = GPR(decode_gpr_gpr1(rd1_value, info), info); in MOVE_BALC() local
10025 return img_format("MOVE.BALC %s, %s, %s", rd1, rtz4, s); in MOVE_BALC()
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