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Searched refs:reg1 (Results 1 – 8 of 8) sorted by relevance

/qemu/target/s390x/
H A Dioinst.c60 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra) in ioinst_handle_xsch() argument
78 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1, uintptr_t ra) in ioinst_handle_csch() argument
96 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra) in ioinst_handle_hsch() argument
735 if (SCHM_REG1_RES(reg1)) { in ioinst_handle_schm()
740 mbk = SCHM_REG1_MBK(reg1); in ioinst_handle_schm()
741 update = SCHM_REG1_UPD(reg1); in ioinst_handle_schm()
742 dct = SCHM_REG1_DCT(reg1); in ioinst_handle_schm()
781 if (RCHP_REG1_RES(reg1)) { in ioinst_handle_rchp()
786 cssid = RCHP_REG1_CSSID(reg1); in ioinst_handle_rchp()
787 chpid = RCHP_REG1_CHPID(reg1); in ioinst_handle_rchp()
[all …]
H A Ds390x-internal.h359 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
360 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
361 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
362 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
364 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
367 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
369 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb, uintptr_t ra);
371 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
373 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
374 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
[all …]
/qemu/pc-bios/s390-ccw/
H A Dcio.h377 register struct subchannel_id reg1 asm ("1") = schid; in stsch_err()
386 : "d" (reg1), "a" (addr) in stsch_err()
393 register struct subchannel_id reg1 asm ("1") = schid; in msch()
401 : "d" (reg1), "a" (addr), "m" (*addr) in msch()
408 register struct subchannel_id reg1 asm ("1") = schid; in msch_err()
417 : "d" (reg1), "a" (addr), "m" (*addr) in msch_err()
432 : "d" (reg1), "a" (addr) in tsch()
439 register struct subchannel_id reg1 asm("1") = schid; in ssch()
448 : "d" (reg1), "a" (addr), "m" (*addr) in ssch()
455 register struct subchannel_id reg1 asm("1") = schid; in csch()
[all …]
/qemu/hw/rtc/
H A Daspeed_rtc.c31 uint32_t reg1 = rtc->reg[COUNTER1]; in aspeed_rtc_calc_offset() local
34 tm.tm_mday = (reg1 >> 24) & 0x1f; in aspeed_rtc_calc_offset()
35 tm.tm_hour = (reg1 >> 16) & 0x1f; in aspeed_rtc_calc_offset()
36 tm.tm_min = (reg1 >> 8) & 0x3f; in aspeed_rtc_calc_offset()
37 tm.tm_sec = (reg1 >> 0) & 0x3f; in aspeed_rtc_calc_offset()
/qemu/hw/ppc/
H A Dppc405_boards.c388 uint8_t reg1; member
401 ret = fpga->reg1; in ref405ep_fpga_readb()
421 fpga->reg1 = value; in ref405ep_fpga_writeb()
443 fpga->reg1 = 0x0F; in ref405ep_fpga_reset()
/qemu/target/mips/tcg/
H A Dnanomips_translate.c.inc993 uint32_t reg1, uint32_t reg2)
1007 gen_store_gpr(tmp1, reg1);
1014 uint32_t reg1, uint32_t reg2, bool eva)
1031 gen_load_gpr(tmp1, reg1);
1044 if (reg1 != 0) {
1045 tcg_gen_movi_tl(cpu_gpr[reg1], 1);
1051 if (reg1 != 0) {
1052 tcg_gen_movi_tl(cpu_gpr[reg1], 0);
/qemu/docs/devel/
H A Dqom.rst49 int reg0, reg1, reg2;
/qemu/target/m68k/
H A Dtranslate.c3204 static void do_exg(TCGv reg1, TCGv reg2) in do_exg() argument
3207 tcg_gen_mov_i32(temp, reg1); in do_exg()
3208 tcg_gen_mov_i32(reg1, reg2); in do_exg()