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Searched refs:reg_value (Results 1 – 12 of 12) sorted by relevance

/qemu/hw/gpio/
H A Daspeed_gpio.c651 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
661 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
681 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
686 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
691 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
696 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
702 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
713 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
718 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
725 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
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H A Dimx_gpio.c152 uint32_t reg_value = 0; in imx_gpio_read() local
160 reg_value = (s->dr & s->gdir) | (s->psr & ~s->gdir); in imx_gpio_read()
164 reg_value = s->gdir; in imx_gpio_read()
168 reg_value = s->psr & ~s->gdir; in imx_gpio_read()
172 reg_value = extract64(s->icr, 0, 32); in imx_gpio_read()
176 reg_value = extract64(s->icr, 32, 32); in imx_gpio_read()
180 reg_value = s->imr; in imx_gpio_read()
184 reg_value = s->isr; in imx_gpio_read()
189 reg_value = s->edge_sel; in imx_gpio_read()
203 DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value); in imx_gpio_read()
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/qemu/hw/timer/
H A Dcadence_ttc.c140 if (is_between(cand, (uint64_t)s->reg_value, next_value)) { in cadence_timer_run()
148 event_interval = next_value - (int64_t)s->reg_value; in cadence_timer_run()
172 x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r); in cadence_timer_sync()
181 if (is_between(m, s->reg_value, x) || in cadence_timer_sync()
182 is_between(m + interval, s->reg_value, x) || in cadence_timer_sync()
183 is_between(m - interval, s->reg_value, x)) { in cadence_timer_sync()
194 s->reg_value = (uint32_t)(x % interval); in cadence_timer_sync()
229 return (uint16_t)(s->reg_value >> 16); in cadence_ttc_read_imp()
309 s->reg_value = 0; in cadence_ttc_write()
431 VMSTATE_UINT32(reg_value, CadenceTimerState),
H A Dimx_gpt.c266 uint32_t reg_value = 0; in imx_gpt_read() local
270 reg_value = s->cr; in imx_gpt_read()
274 reg_value = s->pr; in imx_gpt_read()
278 reg_value = s->sr; in imx_gpt_read()
282 reg_value = s->ir; in imx_gpt_read()
286 reg_value = s->ocr1; in imx_gpt_read()
290 reg_value = s->ocr2; in imx_gpt_read()
294 reg_value = s->ocr3; in imx_gpt_read()
300 reg_value = s->icr1; in imx_gpt_read()
311 reg_value = s->cnt; in imx_gpt_read()
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H A Dimx_epit.c121 uint32_t reg_value = 0; in imx_epit_read() local
125 reg_value = s->cr; in imx_epit_read()
129 reg_value = s->sr; in imx_epit_read()
133 reg_value = s->lr; in imx_epit_read()
137 reg_value = s->cmp; in imx_epit_read()
141 reg_value = ptimer_get_count(s->timer_reload); in imx_epit_read()
150 DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value); in imx_epit_read()
152 return reg_value; in imx_epit_read()
/qemu/hw/acpi/
H A Derst.c176 uint64_t reg_value; member
802 s->reg_value = erst_wr_reg64(addr, s->reg_value, val, size); in erst_reg_write()
820 s->record_offset = s->reg_value; in erst_reg_write()
849 s->reg_value = s->busy_status; in erst_reg_write()
852 s->reg_value = s->command_status; in erst_reg_write()
856 &s->reg_value, false); in erst_reg_write()
859 s->record_identifier = s->reg_value; in erst_reg_write()
868 s->reg_value = le32_to_cpu(s->header->record_size); in erst_reg_write()
874 s->reg_value = in erst_reg_write()
902 val = erst_rd_reg64(addr, s->reg_value, size); in erst_reg_read()
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/qemu/hw/display/
H A Dcirrus_vga.c1087 s->vga.gr[0x31] = reg_value; in cirrus_write_bitblt()
1429 s->cirrus_hidden_dac_data = reg_value; in cirrus_write_hidden_dac()
1517 s->cirrus_shadow_gr0 = reg_value; in cirrus_vga_write_gr()
1521 s->cirrus_shadow_gr1 = reg_value; in cirrus_vga_write_gr()
1537 s->vga.gr[reg_index] = reg_value; in cirrus_vga_write_gr()
1543 s->vga.gr[reg_index] = reg_value; in cirrus_vga_write_gr()
1570 s->vga.gr[reg_index] = reg_value; in cirrus_vga_write_gr()
1589 cirrus_write_bitblt(s, reg_value); in cirrus_vga_write_gr()
1594 reg_index, reg_value); in cirrus_vga_write_gr()
1689 s->vga.cr[s->vga.cr_index] = reg_value; in cirrus_vga_write_cr()
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/qemu/target/i386/whpx/
H A Dwhpx-all.c972 WHV_REGISTER_VALUE reg_value; in whpx_vcpu_configure_single_stepping() local
986 &reg_value); in whpx_vcpu_configure_single_stepping()
999 reg_value.Reg64 |= TF_MASK; in whpx_vcpu_configure_single_stepping()
1001 reg_value.Reg64 &= ~TF_MASK; in whpx_vcpu_configure_single_stepping()
1013 &reg_value); in whpx_vcpu_configure_single_stepping()
1023 reg_value.Reg64 = 0; in whpx_vcpu_configure_single_stepping()
1033 &reg_value); in whpx_vcpu_configure_single_stepping()
1056 &reg_value); in whpx_vcpu_configure_single_stepping()
1072 &reg_value); in whpx_vcpu_configure_single_stepping()
1425 &reg_value); in whpx_vcpu_get_pc()
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H A Dwhpx-apic.c102 WHV_REGISTER_VALUE reg_value = {.Reg64 = val}; in whpx_put_apic_base() local
109 &reg_value); in whpx_put_apic_base()
/qemu/include/hw/timer/
H A Dcadence_ttc.h30 uint32_t reg_value; member
/qemu/tests/plugin/
H A Dinsn.c51 g_autoptr(GByteArray) reg_value = g_byte_array_new(); in vcpu_init()
57 int count = qemu_plugin_read_register(rd->handle, reg_value); in vcpu_init()
/qemu/hw/rtc/
H A Dexynos4210_rtc.c200 uint32_t reg_value) in exynos4210_rtc_update_freq() argument
206 s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value)); in exynos4210_rtc_update_freq()