| /qemu/hw/i2c/ |
| H A D | omap_i2c.c | 39 uint8_t revision; member
167 return s->revision; /* REV */ in omap_i2c_read()
176 if (s->revision >= OMAP2_INTR_REV) in omap_i2c_read()
277 s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f); in omap_i2c_write()
281 if (s->revision < OMAP2_INTR_REV) { in omap_i2c_write()
325 if (s->revision < OMAP2_INTR_REV) { in omap_i2c_write()
338 if (s->revision < OMAP2_INTR_REV) { in omap_i2c_write()
393 if (s->revision >= OMAP2_INTR_REV) { in omap_i2c_write()
491 (s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000); in omap_i2c_realize()
497 if (s->revision >= OMAP2_INTR_REV && !s->iclk) { in omap_i2c_realize()
[all …]
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| /qemu/hw/usb/ |
| H A D | hcd-ehci-pci.c | 29 uint8_t revision; member
190 k->revision = i->revision; in ehci_data_class_init()
202 .revision = 0x10,
207 .revision = 0x03,
213 .revision = 0x03,
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| H A D | hcd-uhci.c | 1278 k->revision = info->revision; in uhci_data_class_init()
1297 .revision = 0x01,
1304 .revision = 0x01,
1311 .revision = 0x03,
1318 .revision = 0x03,
1325 .revision = 0x03,
1332 .revision = 0x03,
1339 .revision = 0x03,
1346 .revision = 0x03,
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| H A D | vt82c686-uhci-pci.c | 34 .revision = 0x01,
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| /qemu/hw/intc/ |
| H A D | arm_gic.c | 412 if (s->revision == REV_11MPCORE) { in gic_set_irq()
623 if (s->revision == REV_11MPCORE) { in gic_acknowledge_irq()
753 if (s->revision == 2) { in gic_set_cpu_control()
759 if (s->revision == 2) { in gic_set_cpu_control()
799 if (s->revision != 2) { in gic_eoi_split()
912 if (s->revision == REV_11MPCORE) { in gic_complete_irq()
1052 } else if (s->revision == 2) { in gic_dist_readb()
1118 if (s->revision == REV_11MPCORE) { in gic_dist_readb()
1142 switch (s->revision) { in gic_dist_readb()
1343 if (s->revision != 2) { in gic_dist_writeb()
[all …]
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| H A D | arm_gic_common.c | 174 s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100); in gic_init_irqs_and_mmio()
217 (s->revision == REV_11MPCORE)) { in arm_gic_common_realize()
224 if (s->revision != 2) { in arm_gic_common_realize()
244 if (s->revision == REV_11MPCORE) { in arm_gic_common_reset_irq_state()
357 DEFINE_PROP_UINT32("revision", GICState, revision, 1),
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| H A D | arm_gicv3_common.c | 152 return cs->gic->revision > 3; in gicv4_needed()
381 if (s->revision != 3 && s->revision != 4) { in arm_gicv3_common_realize()
382 error_setg(errp, "unsupported GIC revision %d", s->revision); in arm_gicv3_common_realize()
472 if (s->revision > 3) { in arm_gicv3_common_realize()
611 DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
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| /qemu/hw/s390x/ |
| H A D | virtio-ccw.c | 115 VMSTATE_INT32(revision, VirtioCcwDevice),
197 uint16_t revision; member
351 dev->revision = 0; in virtio_ccw_cb()
386 if (dev->revision >= 1) { in virtio_ccw_cb()
699 revinfo.revision = be16_to_cpu(revinfo.revision); in virtio_ccw_cb()
710 if (dev->revision >= 0 || in virtio_ccw_cb()
711 revinfo.revision > virtio_ccw_rev_max(dev) || in virtio_ccw_cb()
712 (dev->force_revision_1 && !revinfo.revision)) { in virtio_ccw_cb()
717 dev->revision = revinfo.revision; in virtio_ccw_cb()
730 dev->revision = -1; in virtio_sch_disable_cb()
[all …]
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| H A D | virtio-ccw.h | 70 int revision; member
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| /qemu/hw/i386/xen/ |
| H A D | xen_pvdevice.c | 51 uint8_t revision; member
103 pci_set_byte(pci_conf + PCI_REVISION_ID, d->revision); in xen_pv_realize()
121 DEFINE_PROP_UINT8("revision", XenPVDevice, revision, 0x01),
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| /qemu/tests/qtest/ |
| H A D | acpi-utils.c | 55 uint8_t revision; in acpi_fetch_rsdp_table() local
59 revision = rsdp_table[15 /* Revision offset */]; in acpi_fetch_rsdp_table()
61 switch (revision) { in acpi_fetch_rsdp_table()
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| /qemu/hw/net/ |
| H A D | eepro100.c | 138 uint8_t revision; member
1907 .revision = 0x0e,
1919 .revision = 0x0f,
1929 .revision = 0x01,
1936 .revision = 0x02,
1943 .revision = 0x03,
1950 .revision = 0x04,
1959 .revision = 0x05,
1968 .revision = 0x06,
1977 .revision = 0x07,
[all …]
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| /qemu/qapi/ |
| H A D | acpi.json | 33 # @rev: table revision number (dependent on signature, 1 byte)
39 # @oem_rev: OEM-supplied revision number (4 bytes)
44 # @asl_compiler_rev: revision number of the utility that created the
|
| /qemu/docs/specs/ |
| H A D | ivshmem-spec.rst | 23 The device has vendor ID 1af4, device ID 1110, revision 1. Before
24 QEMU 2.6.0, it had revision 0.
49 revision 0 rather than 1. Guest software should wait for the
82 In revision 0 of the device, Interrupt Status and Mask Register
93 reset. These devices have PCI revision 0 rather than 1.
118 If the peer is a revision 0 device without MSI-X capability, its
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| /qemu/subprojects/ |
| H A D | dtc.wrap | 3 revision = b6910bec11614980a21e46fbccc35934b671bd81
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| H A D | keycodemapdb.wrap | 3 revision = f5772a62ec52591ff6870b7e8ef32482371f22c6
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| H A D | libblkio.wrap | 3 revision = f84cc963a444e4cb34813b2dcfc5bf8526947dc0
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| H A D | libvfio-user.wrap | 3 revision = 0b28d205572c80b568a1003db2c8f37ca333e4d7
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| H A D | slirp.wrap | 3 revision = 26be815b86e8d49add8c9a8b320239b9594ff03d
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| H A D | berkeley-softfloat-3.wrap | 3 revision = b64af41c3276f97f0e181920400ee056b9c88037
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| H A D | berkeley-testfloat-3.wrap | 3 revision = e7af9751d9f9fd3b47911f51a5cfd08af256a9ab
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| /qemu/hw/pci-host/ |
| H A D | uninorth.c | 322 k->revision = 0x00; in unin_main_pci_host_class_init()
350 k->revision = 0x00; in u3_agp_pci_host_class_init()
378 k->revision = 0x00; in unin_agp_pci_host_class_init()
406 k->revision = 0x00; in unin_internal_pci_host_class_init()
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| /qemu/hw/sensor/ |
| H A D | adm1266.c | 89 pmdev->pages[i].revision = ADM1266_PMBUS_REVISION_DEFAULT; in adm1266_exit_reset()
95 pmdev->pages[i].revision = ADM1266_PMBUS_REVISION_DEFAULT; in adm1266_exit_reset()
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| /qemu/hw/char/ |
| H A D | serial-pci-multi.c | 159 pc->revision = 1; in multi_2x_serial_pci_class_initfn()
174 pc->revision = 1; in multi_4x_serial_pci_class_initfn()
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| /qemu/include/hw/net/ |
| H A D | cadence_gem.h | 63 uint32_t revision; member
|