Searched refs:riscv_cpu_update_mip (Results 1 – 6 of 6) sorted by relevance
/qemu/target/riscv/ |
H A D | time_helper.c | 30 riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); in riscv_vstimer_cb() 36 riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1)); in riscv_stimer_cb() 59 riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); in riscv_timer_write_timecmp() 61 riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1)); in riscv_timer_write_timecmp() 69 riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0)); in riscv_timer_write_timecmp() 71 riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0)); in riscv_timer_write_timecmp()
|
H A D | pmu.c | 132 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); in riscv_pmu_incr_ctr_rv32() 171 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); in riscv_pmu_incr_ctr_rv64() 370 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); in pmu_timer_trigger_irq()
|
H A D | cpu.h | 528 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
|
H A D | cpu.c | 1267 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); in riscv_cpu_set_irq() 1275 riscv_cpu_update_mip(env, 1 << irq, in riscv_cpu_set_irq() 1301 riscv_cpu_update_mip(env, MIP_SGEIP, in riscv_cpu_set_irq()
|
H A D | cpu_helper.c | 642 riscv_cpu_update_mip(env, 0, 0); in riscv_cpu_set_virt_enabled() 681 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value) in riscv_cpu_update_mip() function
|
H A D | csr.c | 2442 old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask)); in rmw_mip64() 3490 riscv_cpu_update_mip(env, MIP_SGEIP, in write_hgeie()
|