/qemu/target/microblaze/ |
H A D | mmu.c | 189 if (ext && rn != MMU_R_TLBLO) { in mmu_read() 194 switch (rn) { in mmu_read() 206 if (rn == MMU_R_TLBHI) in mmu_read() 216 r = env->mmu.regs[rn]; in mmu_read() 219 r = env->mmu.regs[rn]; in mmu_read() 240 rn < 3 ? env->mmu.regs[rn] : env->mmu.regs[MMU_R_TLBX]); in mmu_write() 246 if (ext && rn != MMU_R_TLBLO) { in mmu_write() 251 switch (rn) { in mmu_write() 256 if (rn == MMU_R_TLBHI) { in mmu_write() 279 env->mmu.regs[rn] = v; in mmu_write() [all …]
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H A D | mmu.h | 90 uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); 91 void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
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/qemu/target/arm/tcg/ |
H A D | a32.decode | 28 &s_rri_rot s rn rd imm rot 29 &s_rrrr s rd rn rm ra 30 &rrrr rd rn rm ra 31 &rrr_rot rd rn rm rot 32 &rrr rd rn rm 37 &msr_reg rn r mask 39 &msr_bank rn r sysm 42 &ldst_ri p w u rn rt imm 45 &ldrex rn rt rt2 imm 47 &bfi rd rn lsb msb [all …]
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H A D | t32.decode | 26 &s_rrrr !extern s rd rn rm ra 27 &rrrr !extern rd rn rm ra 28 &rrr_rot !extern rd rn rm rot 29 &rrr !extern rd rn rm 34 &msr_reg !extern rn r mask 36 &msr_bank !extern rn r sysm 164 &s_rrr_shr rn=0 258 # bfc is bfi w/ rn=15 346 # Note rn != rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. 613 &tbranch rn rm [all …]
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H A D | a64.decode | 28 &r rn 30 &rri_sf rd rn imm sf 32 &rr_e rd rn esz 33 &rrr_e rd rn rm esz 35 &rrrr_e rd rn rm ra esz 36 &qrr_e q rd rn esz 37 &qrrr_e q rd rn rm esz 112 &rri_log rd rn sf dbm 184 &braz rn m 191 &bra rn rm m [all …]
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H A D | t16.decode | 24 &s_rrr_shr !extern s rn rd rm rs shty 25 &s_rri_rot !extern s rn rd imm rot 26 &s_rrrr !extern s rd rn rm ra 27 &rrr_rot !extern rd rn rm rot 33 &ldst_ri !extern p w u rn rt imm 34 &ldst_block !extern rn i b u w list 48 @xll_noshr ...... .... rm:3 rn:3 \ 72 @ldst_rr ....... rm:3 rn:3 rt:3 \ 88 @ldst_ri_1 ..... imm:5 rn:3 rt:3 \ 90 @ldst_ri_4 ..... ..... rn:3 rt:3 \ [all …]
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H A D | sve.decode | 65 &rr_esz rd rn esz 66 &rri rd rn imm 67 &rr_dbm rd rn dbm 68 &rrri rd rn rm imm 69 &rri_esz rd rn imm esz 71 &rrr_esz rd rn rm esz 73 &rpr_esz rd pg rn esz 74 &rpr_s rd pg rn s 75 &rprr_s rd pg rn rm s 76 &rprr_esz rd pg rn rm esz [all …]
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H A D | translate-a64.c | 1510 set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); in set_btype_for_br() 2758 gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, memop); in gen_store_exclusive() 2827 if (rn == 31) { in gen_compare_and_swap() 2847 if (rn == 31) { in gen_compare_and_swap_pair() 2920 if (a->rn == 31) { in trans_STXR() 2932 if (a->rn == 31) { in trans_LDXR() 4188 if (a->rs == a->rn || a->rs == a->rd || a->rn == a->rd || in do_SET() 4242 if (a->rs == a->rn || a->rs == a->rd || a->rn == a->rd || in do_CPY() 4293 TCGv_i64 tcg_rn = rn_sp ? cpu_reg_sp(s, a->rn) : cpu_reg(s, a->rn); in gen_rri() 8914 EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; in disas_simd_ext() [all …]
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H A D | crypto_helper.c | 187 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in crypto_sha1_3reg() 300 uint64_t *rn = vn; in HELPER() local 303 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in HELPER() 338 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in HELPER() 383 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in HELPER() 439 d1 += S1_512(rm[1]) + cho512(rm[1], rn[0], rn[1]); in HELPER() 499 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in HELPER() 527 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in HELPER() 548 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in crypto_sm3tt() 607 union CRYPTO_STATE d = { .l = { rn[0], rn[1] } }; in do_crypto_sm4e() [all …]
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H A D | translate-sve.c | 1125 TCGv_i64 rn = cpu_reg_sp(s, a->rn); in trans_ADDVL() local 1138 TCGv_i64 rn = cpu_reg_sp(s, a->rn); in trans_ADDSVL() local 1151 TCGv_i64 rn = cpu_reg_sp(s, a->rn); in trans_ADDPL() local 1164 TCGv_i64 rn = cpu_reg_sp(s, a->rn); in trans_ADDSPL() local 1307 if (a->rn == a->rm) { in trans_AND_pppp() 1422 if (!a->s && a->pg == a->rn && a->rn == a->rm) { in trans_ORR_pppp() 2125 TRANS_FEAT(EXT_sve2, aa64_sve2, do_EXT, a->rd, a->rn, (a->rn + 1) % 32, a->imm) 2233 a->rd, a->rn, (a->rn + 1) % 32, a->rm, 0) 2515 if (a->rd != a->rn) { in do_clast_vector() 2696 a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz) [all …]
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H A D | helper-a64.c | 1280 env->xregs[rn] = setsize; in do_setp() 1288 env->xregs[rn] = -setsize; in do_setp() 1328 if (env->xregs[rn] == 0) { in do_setm() 1355 env->xregs[rn] = -setsize; in do_setm() 1418 env->xregs[rn] = -setsize; in do_sete() 1663 env->xregs[rn] = -copysize; in do_cpyp() 1687 env->xregs[rn] = copysize; in do_cpyp() 1726 if (env->xregs[rn] == 0) { in do_cpym() 1741 copysize = env->xregs[rn]; in do_cpym() 1813 if (env->xregs[rn] == 0) { in do_cpye() [all …]
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H A D | neon-ls.decode | 35 VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \ 40 VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \ 47 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \ 49 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \ 51 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \
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H A D | translate.c | 5184 .rn = a->rn, .rt = a->rt, .imm = a->imm in trans_LDRD_ri_t32() 5220 .rn = a->rn, .rt = a->rt, .imm = a->imm in trans_STRD_ri_t32() 5674 if (a->rn == 15) { in trans_BFCI() 5898 if (a->rn != 15) { in op_xta() 6645 if (a->rn == 13 || a->rn == 15) { in trans_DLS() 6684 if (a->rn == 13 || a->rn == 15) { in trans_WLS() 6892 if (!dc_isar_feature(aa32_mve, s) || a->rn == 13 || a->rn == 15) { in trans_VCTP() 7214 TCGv_i32 rn, rm; in trans_CSEL() local 7234 if (a->rn == 15) { in trans_CSEL() 7237 load_reg_var(s, rn, a->rn); in trans_CSEL() [all …]
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H A D | sme.decode | 43 &ldst esz rs pg rn rm za_imm v:bool st:bool 45 LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ 47 LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ 50 &ldstr rv rn imm 51 @ldstr ....... ... . ...... .. ... rn:5 . imm:4 \
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H A D | translate-m-nocp.c | 86 fptr = load_reg(s, a->rn); in trans_VLLDM_VLSTM() 640 addr = load_reg(s, a->rn); in fp_sysreg_to_memory() 645 if (s->v8m_stackcheck && a->rn == 13 && a->w) { in fp_sysreg_to_memory() 659 store_reg(s, a->rn, addr); in fp_sysreg_to_memory() 679 addr = load_reg(s, a->rn); in memory_to_fp_sysreg() 684 if (s->v8m_stackcheck && a->rn == 13 && a->w) { in memory_to_fp_sysreg() 699 store_reg(s, a->rn, addr); in memory_to_fp_sysreg() 709 if (a->rn == 15) { in trans_VLDR_sysreg() 720 if (a->rn == 15) { in trans_VSTR_sysreg()
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H A D | translate-neon.c | 423 base = load_reg(s, rn); in gen_neon_ldst_base_update() 431 store_reg(s, rn, base); in gen_neon_ldst_base_update() 1753 tcg_gen_addi_i64(rn, rn, 1u << 31); in gen_narrow_round_high_u32() 1773 TCGv_i32 rn, rm; in DO_NARROW_3D() local 1801 rn = tcg_temp_new_i32(); in DO_NARROW_3D() 1805 opfn(rd0, rn, rm); in DO_NARROW_3D() 1809 opfn(rd1, rn, rm); in DO_NARROW_3D() 2308 TCGv_i32 scalar, rn, rd; in do_vqrdmlah_2sc() local 2339 rn = tcg_temp_new_i32(); in do_vqrdmlah_2sc() 2383 TCGv_i32 scalar, rn; in do_2scalar_long() local [all …]
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H A D | translate-mve.c | 158 if (a->rn == 15 || (a->rn == 13 && a->w)) { in do_ldst() 383 TCGv_i32 rn; in do_vldst_il() local 387 !fn || (a->rn == 13 && a->w) || a->rn == 15) { in do_vldst_il() 395 rn = load_reg(s, a->rn); in do_vldst_il() 403 tcg_gen_addi_i32(rn, rn, addrinc); in do_vldst_il() 404 store_reg(s, a->rn, rn); in do_vldst_il() 1858 rn = load_reg(s, a->rn); in do_vidup() 1859 fn(rn, tcg_env, qd, rn, tcg_constant_i32(a->imm)); in do_vidup() 1860 store_reg(s, a->rn, rn); in do_vidup() 1892 rn = load_reg(s, a->rn); in do_viwdup() [all …]
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H A D | vfp.decode | 83 VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp 84 VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp 85 VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp 95 VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \ 97 VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \ 100 VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \ 102 VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
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H A D | mve.decode | 40 &vldr_vstr rn qd imm p a w size l u 46 &vidup qd rn size imm 47 &viwdup qd rn rm size imm 53 &vldst_sg qd qm rn size msize os 55 &vldst_il qd rn size pat w 60 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 62 @vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr 64 @vldst_sg .... .... .... rn:4 .... ... size:2 ... ... os:1 &vldst_sg \ 72 @vldst_il .... .... .. w:1 . rn:4 .... ... size:2 pat:2 ..... &vldst_il \ 408 qd=%qd imm=%imm_vidup rn=%vidup_rn &vidup [all …]
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/qemu/tcg/arm/ |
H A D | tcg-target.c.inc | 588 tcg_out_bx_reg(s, cond, rn); 634 (rn << 16) | (rt << 12) | imm12); 662 TCGReg rn, int imm8) 711 TCGReg rn, int imm8) 753 TCGReg rn, TCGReg rm) 759 TCGReg rn, TCGReg rm) 1022 /* bfi becomes bfc with rn == 15. */ 1290 static uint32_t encode_vn(TCGReg rn) 1292 tcg_debug_assert(rn >= TCG_REG_Q0); 1293 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); [all …]
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/qemu/tests/tcg/loongarch64/ |
H A D | test_pcadd.c | 10 uint64_t rm, rn; \ 18 rn = ((0x12345UL - 0x104) << a) & ~0xfff; \ 20 rn = ((0x12345UL - 0x104) << a) + 4; \ 22 assert(rm == rn); \
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/qemu/pc-bios/vof/ |
H A D | entry.S | 1 #define LOAD32(rn, name) \ argument 2 lis rn,name##@h; \ 3 ori rn,rn,name##@l
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/qemu/tcg/aarch64/ |
H A D | tcg-target.c.inc | 696 tcg_out32(s, insn | rn << 5); 732 | rn << 5 | rd); 741 | rn << 5 | rd); 815 | (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5); 1365 tcg_out_extr(s, ext, rd, rn, rn, m & max); 1372 tcg_out_extr(s, ext, rd, rn, rn, -m & max); 1381 tcg_out_bfm(s, ext, rd, rn, a, b); 1548 tcg_out_ext32s(s, rd, rn); 1561 tcg_out_uxt(s, MO_8, rd, rn); 1566 tcg_out_uxt(s, MO_16, rd, rn); [all …]
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/qemu/util/ |
H A D | range.c | 83 Range *r, *rn; in range_inverse_array() local 104 rn = (Range *)l->next->data; in range_inverse_array() 108 if (range_compare(r, rn)) { in range_inverse_array() 110 MIN(range_lob(rn) - 1, high)); in range_inverse_array()
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/qemu/disas/ |
H A D | sh4.c | 1176 fprintf_fn (stream, "@r%d", rn); in print_movxy() 1183 fprintf_fn (stream, "@r%d+", rn); in print_movxy() 1624 int rn = 0; in print_insn_sh() local 1762 rn = nibs[n]; in print_insn_sh() 1770 rn = (nibs[n] & 0xc) >> 2; in print_insn_sh() 1773 rn = (nibs[n] & 0xc) >> 2; in print_insn_sh() 1781 rn = nibs[n]; in print_insn_sh() 1782 if ((rn & 0xc) != 4) in print_insn_sh() 1784 rn = rn & 0x3; in print_insn_sh() 1785 rn |= (!(rn & 2)) << 2; in print_insn_sh() [all …]
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