/qemu/target/riscv/ |
H A D | crypto_helper.c | 34 uint8_t si = rs2 >> shamt; in aes32_operation() 60 return aes32_operation(shamt, rs1, rs2, true, true); in HELPER() 66 return aes32_operation(shamt, rs1, rs2, true, false); in HELPER() 72 return aes32_operation(shamt, rs1, rs2, false, true); in HELPER() 88 t.d[!HOST_BIG_ENDIAN] = rs2; in HELPER() 98 t.d[!HOST_BIG_ENDIAN] = rs2; in HELPER() 108 t.d[!HOST_BIG_ENDIAN] = rs2; in HELPER() 122 t.d[!HOST_BIG_ENDIAN] = rs2; in HELPER() 130 uint64_t RS2 = rs2; in HELPER() 177 uint32_t sb_in = (uint8_t)(rs2 >> shamt); in HELPER() [all …]
|
H A D | fpu_helper.c | 125 float16 frs2 = check_nanbox_h(env, rs2); in do_fmadd_h() 135 float32 frs2 = check_nanbox_s(env, rs2); in do_fmadd_s() 221 float32 frs2 = check_nanbox_s(env, rs2); in helper_fadd_s() 228 float32 frs2 = check_nanbox_s(env, rs2); in helper_fsub_s() 235 float32 frs2 = check_nanbox_s(env, rs2); in helper_fmul_s() 242 float32 frs2 = check_nanbox_s(env, rs2); in helper_fdiv_s() 249 float32 frs2 = check_nanbox_s(env, rs2); in helper_fmin_s() 258 float32 frs2 = check_nanbox_s(env, rs2); in helper_fminm_s() 266 float32 frs2 = check_nanbox_s(env, rs2); in helper_fmax_s() 275 float32 frs2 = check_nanbox_s(env, rs2); in helper_fmaxm_s() [all …]
|
H A D | bitmanip_helper.c | 27 target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) in HELPER() 32 if ((rs2 >> i) & 1) { in HELPER() 40 target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2) in HELPER() 45 if ((rs2 >> i) & 1) { in HELPER() 106 static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2, in do_xperm() argument 115 pos = ((rs2 >> i) & mask) << sz_log2; in do_xperm() 123 target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2) in HELPER() 125 return do_xperm(rs1, rs2, 2); in HELPER() 128 target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2) in HELPER() 130 return do_xperm(rs1, rs2, 3); in HELPER()
|
H A D | insn16.decode | 56 &r rd rs1 rs2 !extern 58 &s imm rs1 rs2 !extern 60 &b imm rs2 rs1 !extern 64 &r2_s rs1 rs2 !extern 70 @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd 75 @cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3 80 @cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0 85 @c_sqsp ... . ..... ..... .. &s imm=%uimm_6bit_sq rs1=2 rs2=%rs2_5 86 @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5 87 @c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5 [all …]
|
H A D | insn32.decode | 21 %rs2 20:5 44 &b imm rs2 rs1 47 &r rd rs1 rs2 49 &r2_s rs1 rs2 50 &s imm rs1 rs2 53 &atomic aq rl rs2 rs1 rd 54 &rmrr vm rd rs1 rs2 55 &rmr vm rd rs2 57 &rnfvm vm rd rs1 rs2 nf 58 &k_aes shamt rs2 rs1 rd [all …]
|
H A D | xthead.decode | 18 %rs2 20:5 26 &r rd rs1 rs2 !extern 31 &th_memidx rd rs1 rs2 imm2 36 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 37 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 43 @th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %rs2 %imm2 53 # is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
|
H A D | XVentanaCondOps.decode | 13 %rs2 20:5 18 &r rd rs1 rs2 !extern 21 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
|
/qemu/target/sparc/ |
H A D | insns.decode | 47 &r_r_r rd rs1 rs2 84 &r_r_r_r rd rs1 rs2 rs3 243 &shiftr rd rs1 rs2 x:bool 345 rd=%dfp_rd rs2=%dfp_rs2 347 rd=%qfp_rd rs2=%qfp_rs2 351 rd=%dfp_rd rs2=%dfp_rs2 353 rd=%qfp_rd rs2=%qfp_rs2 357 rd=%dfp_rd rs2=%dfp_rs2 359 rd=%qfp_rd rs2=%qfp_rs2 363 rs1=%dfp_rs1 rs2=%dfp_rs2 [all …]
|
H A D | vis_helper.c | 25 target_ulong helper_array8(target_ulong rs1, target_ulong rs2) in helper_array8() argument 34 target_ulong n = MIN(rs2 & 7, 5); in helper_array8() 391 uint32_t helper_fpack16(uint64_t gsr, uint64_t rs2) in helper_fpack16() argument 399 int16_t src = rs2 >> (byte * 16); in helper_fpack16() 412 uint64_t helper_fpack32(uint64_t gsr, uint64_t rs1, uint64_t rs2) in helper_fpack32() argument 421 int32_t src = rs2 >> (word * 32); in helper_fpack32() 434 uint32_t helper_fpackfix(uint64_t gsr, uint64_t rs2) in helper_fpackfix() argument 442 int32_t src = rs2 >> (word * 32); in helper_fpackfix()
|
/qemu/target/riscv/insn_trans/ |
H A D | trans_rvzfh.c.inc | 242 if (a->rs1 == a->rs2) { /* FMOV */ 271 TCGv_i64 rs1, rs2, mask; 286 if (a->rs1 == a->rs2) { /* FNEG */ 290 rs2 = tcg_temp_new_i64(); 295 tcg_gen_mov_i64(rs2, src2); 303 tcg_gen_not_i64(rs2, rs2); 304 tcg_gen_andc_i64(rs2, rs2, mask); 318 TCGv_i64 rs1, rs2; 333 if (a->rs1 == a->rs2) { /* FABS */ 337 rs2 = tcg_temp_new_i64(); [all …]
|
H A D | trans_rvf.c.inc | 240 if (a->rs1 == a->rs2) { /* FMOV */ 269 TCGv_i64 rs1, rs2, mask; 283 if (a->rs1 == a->rs2) { /* FNEG */ 287 rs2 = tcg_temp_new_i64(); 291 tcg_gen_mov_i64(rs2, src2); 299 tcg_gen_nor_i64(rs2, rs2, mask); 301 tcg_gen_or_i64(dest, dest, rs2); 314 TCGv_i64 rs1, rs2; 329 if (a->rs1 == a->rs2) { /* FABS */ 333 rs2 = tcg_temp_new_i64(); [all …]
|
H A D | trans_rvd.c.inc | 90 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); 108 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); 126 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); 144 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); 162 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); 245 if (a->rs1 == a->rs2) { /* FMOV */ 266 if (a->rs1 == a->rs2) { /* FNEG */ 288 if (a->rs1 == a->rs2) { /* FABS */ 369 REQUIRE_EVEN(ctx, a->rs1 | a->rs2); 384 REQUIRE_EVEN(ctx, a->rs1 | a->rs2); [all …]
|
H A D | trans_rvzacas.c.inc | 29 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 81 * Encodings with odd numbered registers specified in rs2 and rd are 84 if ((a->rs2 | a->rd) & 1) { 90 TCGv_i64 src2 = get_gpr_pair(ctx, a->rs2); 119 * Encodings with odd numbered registers specified in rs2 and rd are 122 if ((a->rs2 | a->rd) & 1) { 130 TCGv_i64 src2l = get_gpr(ctx, a->rs2, EXT_NONE); 131 TCGv_i64 src2h = get_gpr(ctx, a->rs2 == 0 ? 0 : a->rs2 + 1, EXT_NONE);
|
H A D | trans_rvvk.c.inc | 28 return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \ 188 vext_check_ss(s, a->rd, a->rs2, a->vm); 196 vext_check_ss(s, a->rd, a->rs2, a->vm); 283 require_align(a->rs2, s->lmul) && 296 return vaes_check_overlap(s, a->rd, a->rs2) && 359 require_align(a->rs2, s->lmul); 371 require_align(a->rs2, s->lmul); 429 !is_overlapped(a->rd, mult, a->rs2, mult) && 541 vext_check_ss(s, a->rd, a->rs2, a->vm) && 578 require_align(a->rs2, s->lmul); [all …]
|
H A D | trans_rvzfa.c.inc | 188 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); 205 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); 222 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); 239 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); 256 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); 273 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); 441 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); 456 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); 471 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); 486 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); [all …]
|
H A D | trans_rvv.c.inc | 214 TCGv s2 = get_gpr(s, a->rs2, EXT_ZERO); 819 stride = get_gpr(s, rs2, EXT_NONE); 1710 vext_check_ms(s, a->rd, a->rs2); 1898 vext_check_ms(s, a->rd, a->rs2); 2006 /* vmv.v.v has rs2 = 0 and vm = 1 */ 2036 /* vmv.v.x has rs2 = 0 and vm = 1 */ 2598 vext_check_ms(s, a->rd, a->rs2); 2904 vext_check_reduction(s, a->rs2); 3461 (a->rd != a->rs2) && 3536 (a->rd != a->rs2) && [all …]
|
H A D | trans_xthead.c.inc | 93 TCGv src2 = get_gpr(ctx, rs2, EXT_NONE); 111 * th.addsl shifts rs2. 315 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 325 /* th.mveqz: "if (rs2 == 0) rd = rs1;" */ 332 /* th.mvnez: "if (rs2 != 0) rd = rs1;" */ 343 * If !zext_offs, then address is rs1 + (rs2 << imm2). 487 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 504 /* th.mula: "rd = rd + rs1 * rs2" */ 519 /* th.mulaw: "rd = sext.w(rd + rs1 * rs2)" */ 528 /* th.muls: "rd = rd - rs1 * rs2" */ [all …]
|
H A D | trans_rvbf16.c.inc | 82 vreg_ofs(ctx, a->rs2), tcg_env, 107 vreg_ofs(ctx, a->rs2), tcg_env, 123 vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) { 134 vreg_ofs(ctx, a->rs2), tcg_env, 150 vext_check_ds(ctx, a->rd, a->rs2, a->vm)) { 158 return opfvf_trans(a->rd, a->rs1, a->rs2, data,
|
/qemu/tests/tcg/tricore/asm/ |
H A D | macros.h | 115 #define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \ 118 LI(DREG_RS2, rs2); \ 124 #define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \ 127 LI(DREG_RS2, rs2); \ 132 #define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \ 135 LI(DREG_RS2, rs2); \ 141 #define TEST_D_DDI(insn, num, result, rs1, rs2, imm) \ 144 LI(DREG_RS2, rs2); \ 157 #define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \ 165 #define TEST_D_DDII(insn, num, result, rs1, rs2, imm1, imm2) \ [all …]
|
H A D | test_insert.S | 5 # insn num result rs1 imm1 rs2 imm2 14 # insn num result rs1 rs2 pos width
|
H A D | test_dextr.S | 5 # insn num result rs1 rs2 imm 40 # insn num result rs1 rs2 rs3
|
/qemu/target/rx/ |
H A D | insns.decode | 26 &rrr rd rs rs2 27 &rri rd imm rs2 30 &mr rs ld mi rs2 108 # ADD rs, rs2, rd 214 # CMP #imm, rs2 217 # CMP rs, rs2 302 # MACHI rs, rs2 304 # MACLO rs, rs2 408 # MULHI rs, rs2 410 # MULLO rs, rs2 [all …]
|
H A D | disas.c | 394 prt("pushm\tr%d-r%d", a->rs, a->rs2); in trans_PUSHM() 567 if (a->imm < 0x10 && a->rs2 == a->rd) { in trans_ADD_irr() 595 prt_ir(ctx, "cmp", a->imm, a->rs2); in trans_CMP_ir() 704 prt("mul\tr%d,r%d,r%d", a->rs, a->rs2, a->rd); in trans_MUL_rrr() 773 if (a->rs2 != a->rd) { in trans_SHLL_irr() 792 if (a->rs2 != a->rd) { in trans_SHAR_irr() 811 if (a->rs2 != a->rd) { in trans_SHLR_irr() 1023 prt("mulhi\tr%d,r%d", a->rs, a->rs2); in trans_MULHI() 1030 prt("mullo\tr%d, r%d", a->rs, a->rs2); in trans_MULLO() 1037 prt("machi\tr%d, r%d", a->rs, a->rs2); in trans_MACHI() [all …]
|
H A D | translate.c | 681 if (a->rs == 0 || a->rs >= a->rs2) { in trans_PUSHM() 685 r = a->rs2; in trans_PUSHM() 1073 rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); in trans_CMP_ir() 1392 shiftr_imm(a->rd, a->rs2, a->imm, 1); in trans_SHAR_irr() 1407 shiftr_imm(a->rd, a->rs2, a->imm, 0); in trans_SHLR_irr() 1707 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); in rx_mul64hi() 1720 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); in rx_mul64lo() 1729 rx_mul64hi(cpu_acc, a->rs, a->rs2); in trans_MULHI() 1736 rx_mul64lo(cpu_acc, a->rs, a->rs2); in trans_MULLO() 1745 rx_mul64hi(tmp, a->rs, a->rs2); in trans_MACHI() [all …]
|
/qemu/disas/ |
H A D | riscv.c | 4329 dec->rs2 = rv_ireg_zero; in decode_inst_operands() 4335 dec->rs2 = rv_ireg_zero; in decode_inst_operands() 4341 dec->rs2 = rv_ireg_zero; in decode_inst_operands() 4347 dec->rs2 = rv_ireg_zero; in decode_inst_operands() 4353 dec->rs2 = rv_ireg_zero; in decode_inst_operands() 4400 dec->rs2 = rv_ireg_zero; in decode_inst_operands() 4414 dec->rs2 = rv_ireg_zero; in decode_inst_operands() 4419 dec->rs2 = rv_ireg_zero; in decode_inst_operands() 4424 dec->rs2 = rv_ireg_zero; in decode_inst_operands() 4699 uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2; in check_constraints() local [all …]
|