/qemu/tests/tcg/xtensa/ |
H A D | test_timer.S | 9 rsr \delta, ccount 10 rsr \target, ccount 21 rsr a3, ccount 22 rsr a4, ccount 27 rsr a3, ccount 28 rsr a4, ccount 33 rsr a3, ccount 66 rsr a2, interrupt 77 rsr a3, interrupt 83 rsr a2, interrupt [all …]
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H A D | test_phys_mem.S | 33 rsr a3, excvaddr 35 rsr a3, epc1 37 rsr a3, exccause 51 rsr a3, excvaddr 54 rsr a3, epc1 56 rsr a3, exccause 70 rsr a3, excvaddr 73 rsr a3, epc1 91 rsr a3, epc1 110 rsr a3, epc1 [all …]
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H A D | test_mmu.S | 157 rsr a3, epc1 166 rsr a2, ps 206 rsr a2, epc1 215 rsr a2, ps 239 rsr a2, depc 245 rsr a2, ps 279 rsr a2, epc1 299 rsr a2, epc1 321 rsr a2, epc1 412 rsr a2, \sr [all …]
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H A D | test_windowed.S | 36 rsr a2, epc1 42 rsr a2, windowbase 45 rsr a2, ps 56 rsr a2, ps 100 rsr a2, epc1 106 rsr a2, ps 116 rsr a2, ps 149 rsr a2, ps 181 rsr a2, epc1 266 rsr a2, ps [all …]
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H A D | test_interrupt.S | 58 rsr a2, interrupt 62 rsr a2, interrupt 67 rsr a2, ps 71 rsr a2, exccause 78 rsr a2, ps 80 rsr a4, ps 99 rsr a3, interrupt 184 rsr a2, ps 210 rsr a2, ps 229 rsr a3, ps [all …]
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H A D | test_break.S | 22 rsr a2, ps 27 rsr a2, EPC_DEBUG 30 rsr a2, debugcause 46 rsr a2, ps 51 rsr a2, EPC_DEBUG 54 rsr a2, debugcause 85 rsr a2, ps 90 rsr a2, EPC_DEBUG 93 rsr a2, debugcause 112 rsr a2, ps [all …]
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H A D | test_sar.S | 28 rsr a3, sar 43 rsr a3, sar 58 rsr a3, sar 73 rsr a3, sar 88 rsr a3, sar 102 rsr a3, sar
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H A D | test_boolean.S | 11 rsr a3, br 14 rsr a3, br 17 rsr a3, br 20 rsr a3, br
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H A D | test_mac16.S | 11 rsr a4, ACCLO 14 rsr a4, ACCHI 130 rsr a3, m0 136 rsr a3, m1 150 rsr a3, m2 156 rsr a3, m3 193 rsr a2, m1 207 rsr a2, m2 221 rsr a2, m1 236 rsr a2, m2
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H A D | test_load_store.S | 48 rsr a6, exccause 51 rsr a6, epc1 54 rsr a6, excvaddr 128 rsr a6, exccause 131 rsr a6, epc1 134 rsr a6, excvaddr
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H A D | test_cache.S | 50 rsr a2, epc1 53 rsr a2, excvaddr 55 rsr a2, exccause
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H A D | test_fp_cpenable.S | 18 rsr a3, epc1 21 rsr a3, exccause
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H A D | test_quo.S | 67 rsr a2, exccause 69 rsr a2, epc1 142 rsr a2, exccause 144 rsr a2, epc1
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H A D | test_rem.S | 67 rsr a2, exccause 69 rsr a2, epc1 142 rsr a2, exccause 144 rsr a2, epc1
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H A D | test_sr.S | 37 rsr a2, exccause 39 rsr a2, epc1 47 test_sr_op \sym, \mask & 1, rsr, HI_RSR, \sr
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H A D | test_loop.S | 19 rsr a2, lcount 65 rsr a4, ps
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/qemu/target/xtensa/core-fsf/ |
H A D | xtensa-modules.c.inc | 8962 return 125; /* rsr.lbeg */ 8964 return 119; /* rsr.lend */ 8968 return 128; /* rsr.sar */ 8986 return 228; /* rsr.ddr */ 9000 return 134; /* rsr.176 */ 9002 return 139; /* rsr.epc1 */ 9004 return 145; /* rsr.epc2 */ 9006 return 151; /* rsr.epc3 */ 9008 return 157; /* rsr.epc4 */ 9018 return 135; /* rsr.208 */ [all …]
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/qemu/target/xtensa/core-dc232b/ |
H A D | xtensa-modules.c.inc | 12520 return 127; /* rsr.lbeg */ 12522 return 121; /* rsr.lend */ 12526 return 130; /* rsr.sar */ 12536 return 292; /* rsr.m0 */ 12538 return 295; /* rsr.m1 */ 12540 return 298; /* rsr.m2 */ 12542 return 301; /* rsr.m3 */ 12558 return 350; /* rsr.ddr */ 12572 return 136; /* rsr.176 */ 12602 return 137; /* rsr.208 */ [all …]
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/qemu/hw/char/ |
H A D | pl011.c | 177 s->rsr = c >> 8; in pl011_read() 183 r = s->rsr; in pl011_read() 368 s->rsr = 0; in pl011_write() 546 VMSTATE_UINT32(rsr, PL011State), 604 s->rsr = 0; in pl011_reset()
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/qemu/hw/net/ |
H A D | ne2000.c | 225 s->rsr = ENRSR_RXOK; /* receive status */ in ne2000_receive() 228 s->rsr |= ENRSR_PHY; in ne2000_receive() 229 p[0] = s->rsr; in ne2000_receive() 401 ret = s->rsr; in ne2000_ioport_read() 620 VMSTATE_UINT8(rsr, NE2000State),
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/qemu/target/xtensa/core-sample_controller/ |
H A D | xtensa-modules.c.inc | 8973 { "rsr.sar", ICLASS_xt_iclass_rsr_sar, 9009 { "rsr.ps", ICLASS_xt_iclass_rsr_ps, 9018 { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, 9036 { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, 9054 { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, 9072 { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, 9090 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, 9108 { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, 9126 { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, 9144 { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, [all …]
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/qemu/hw/m68k/ |
H A D | mcf5206.c | 172 uint8_t rsr; member 283 s->rsr = 0x80; in m5206_mbar_reset() 305 case 0x40: return s->rsr; in m5206_mbar_read() 357 s->rsr &= ~value; in m5206_mbar_write()
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/qemu/target/xtensa/core-dc233c/ |
H A D | xtensa-modules.c.inc | 11759 { "rsr.lend", ICLASS_xt_iclass_rsr_lend, 11777 { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, 11786 { "rsr.sar", ICLASS_xt_iclass_rsr_sar, 11804 { "rsr.176", ICLASS_xt_iclass_rsr_176, 11810 { "rsr.208", ICLASS_xt_iclass_rsr_208, 11813 { "rsr.ps", ICLASS_xt_iclass_rsr_ps, 12278 { "rsr.m0", ICLASS_xt_iclass_rsr_m0, 12287 { "rsr.m1", ICLASS_xt_iclass_rsr_m1, 12296 { "rsr.m2", ICLASS_xt_iclass_rsr_m2, 12305 { "rsr.m3", ICLASS_xt_iclass_rsr_m3, [all …]
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/qemu/target/xtensa/core-de212/ |
H A D | xtensa-modules.c.inc | 11119 { "rsr.lend", ICLASS_xt_iclass_rsr_lend, 11137 { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, 11146 { "rsr.sar", ICLASS_xt_iclass_rsr_sar, 11182 { "rsr.ps", ICLASS_xt_iclass_rsr_ps, 11191 { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, 11209 { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, 11647 { "rsr.m0", ICLASS_xt_iclass_rsr_m0, 11656 { "rsr.m1", ICLASS_xt_iclass_rsr_m1, 11665 { "rsr.m2", ICLASS_xt_iclass_rsr_m2, 11674 { "rsr.m3", ICLASS_xt_iclass_rsr_m3, [all …]
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/qemu/include/hw/char/ |
H A D | pl011.h | 38 uint32_t rsr; member
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