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Searched refs:sar (Results 1 – 25 of 30) sorted by relevance

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/qemu/tests/tcg/xtensa/
H A Dtest_sar.S3 test_suite sar
24 wsr a2, sar
28 rsr a3, sar
33 test sar
34 tests_sar sar
43 rsr a3, sar
58 rsr a3, sar
73 rsr a3, sar
88 rsr a3, sar
102 rsr a3, sar
H A Dtest_shift.S96 wsr a2, sar
124 wsr a2, sar
154 wsr a2, sar
185 wsr a2, sar
H A Dtest_sr.S214 test_sr sar, 1
/qemu/linux-user/hppa/
H A Dtarget_syscall.h15 target_ulong sar; member
/qemu/linux-user/xtensa/
H A Dtarget_syscall.h26 xtensa_reg_t sar; /* 44 */ member
/qemu/target/xtensa/core-lx106/
H A Dgdb-config.c.inc40 XTREG( 17, 68, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc6109 { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
6112 { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
6115 { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc94 XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar,
H A Dxtensa-modules.c.inc11144 { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
11147 { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
11150 { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
12334 return 132; /* xsr.sar */
12526 return 130; /* rsr.sar */
12663 return 131; /* wsr.sar */
/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc57 XTREG( 33,132, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc8973 { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
8976 { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
8979 { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc61 XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar, 0, 0, 0, 0, 0, 0)
H A Dxtensa-modules.c.inc11786 { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
11789 { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
11792 { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc60 XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc11146 { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
11149 { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
11152 { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc59 XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc59 XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
/qemu/target/xtensa/core-fsf/
H A Dxtensa-modules.c.inc8098 { "rsr.sar", 86 /* xt_iclass_rsr.sar */,
8101 { "wsr.sar", 87 /* xt_iclass_wsr.sar */,
8104 { "xsr.sar", 88 /* xt_iclass_xsr.sar */,
8829 return 130; /* xsr.sar */
8968 return 128; /* rsr.sar */
9069 return 129; /* wsr.sar */
/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc59 XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc16408 { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
16411 { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
16414 { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
/qemu/target/xtensa/core-dsp3400/
H A Dgdb-config.c.inc59 XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
/qemu/tcg/
H A Doptimize.c2475 CASE_OP_32_64(sar): in fold_shift()
2912 CASE_OP_32_64(sar): in tcg_optimize()
/qemu/tcg/tci/
H A Dtcg-target.c.inc752 CASE_32_64(sar)
/qemu/tests/tcg/i386/
H A Dtest-i386.c137 #define OP sar
/qemu/target/xtensa/
H A Dtranslate.c2312 gen_shift(sar); in translate_sra()
2702 gen_translate_xsr(sar)

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