Home
last modified time | relevance | path

Searched refs:scalar (Results 1 – 25 of 28) sorted by relevance

12

/qemu/target/arm/tcg/
H A Dsve.decode256 # Two registers and a scalar by N-bit index
562 # SVE insert SIMD&FP scalar register
1152 # SVE contiguous load (scalar plus scalar)
1155 # SVE contiguous first-fault load (scalar plus scalar)
1164 # SVE contiguous non-temporal load (scalar plus scalar)
1166 # SVE load multiple structures (scalar plus scalar)
1176 # SVE load and broadcast quadword (scalar plus scalar)
1198 # SVE contiguous prefetch (scalar plus scalar)
1251 # SVE contiguous store (scalar plus scalar)
1268 # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0)
[all …]
H A Dmve.decode43 &2scalar qd qn rm size
92 @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
93 @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
152 @2op_fp_scalar .... .... .... .... .... .... .... rm:4 &2scalar \
501 VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar
515 VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar
523 VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar
570 VQRDMLAH 1110 1110 0 . .. ... 0 ... 0 1110 . 100 .... @2scalar
571 VQRDMLASH 1110 1110 0 . .. ... 0 ... 1 1110 . 100 .... @2scalar
572 VQDMLAH 1110 1110 0 . .. ... 0 ... 0 1110 . 110 .... @2scalar
[all …]
H A Dneon-dp.decode389 # decode: 0b11 for VEXT, two-reg-misc, VTBL, and duplicate-scalar;
391 # two-reg-and-scalar insn groups (where size cannot be 0b11). This
580 # 2-regs-plus-scalar grouping:
583 &2scalar vm vn vd size q
585 @2scalar .... ... q:1 . . size:2 .... .... .... . . . . .... \
586 &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp
589 &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
591 VMLA_2sc 1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar
592 VMLA_F_2sc 1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar
599 VMLS_2sc 1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar
[all …]
H A Dsme-fa64.decode41 OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar)
42 OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar, FP16)
43 OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar)
44 OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar, FP16)
H A Dneon-shared.decode26 # 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
H A Dtranslate-neon.c2117 TCGv_i32 scalar, tmp; in do_2scalar() local
2143 scalar = neon_get_scalar(a->size, a->vm); in do_2scalar()
2148 opfn(tmp, tmp, scalar); in do_2scalar()
2308 TCGv_i32 scalar, rn, rd; in do_vqrdmlah_2sc() local
2338 scalar = neon_get_scalar(a->size, a->vm); in do_vqrdmlah_2sc()
2345 opfn(rd, tcg_env, rn, scalar, rd); in do_vqrdmlah_2sc()
2383 TCGv_i32 scalar, rn; in do_2scalar_long() local
2409 scalar = neon_get_scalar(a->size, a->vm); in do_2scalar_long()
2415 opfn(rn0_64, rn, scalar); in do_2scalar_long()
2419 opfn(rn1_64, rn, scalar); in do_2scalar_long()
H A Da64.decode703 ### Advanced SIMD scalar copy
716 ### Advanced SIMD scalar three same
785 ### Advanced SIMD scalar pairwise
945 ### Advanced SIMD scalar x indexed element
H A Dvfp.decode57 # VMOV scalar to general-purpose register; note that this does
H A Dtranslate-a64.c9021 static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, in handle_simd_qshl() argument
9031 assert(!(scalar && is_q)); in handle_simd_qshl()
9033 if (!scalar) { in handle_simd_qshl()
9097 MemOp memop = scalar ? size : MO_32; in handle_simd_qshl()
9098 int maxpass = scalar ? 1 : is_q ? 4 : 2; in handle_simd_qshl()
9105 if (scalar) { in handle_simd_qshl()
9124 if (!scalar) { in handle_simd_qshl()
9918 static void handle_2misc_narrow(DisasContext *s, bool scalar, in handle_2misc_narrow() argument
9928 int passes = scalar ? 1 : 2; in handle_2misc_narrow()
9930 if (scalar) { in handle_2misc_narrow()
[all …]
H A Dtranslate-sve.c3731 TCGv_i64 scalar, gen_helper_sve_fp2scalar *fn) in do_fp_scalar() argument
3746 fn(t_zd, t_zn, t_pg, scalar, status, desc); in do_fp_scalar()
5106 int scale, TCGv_i64 scalar, int msz, bool is_write, in do_mem_zpz() argument
5119 fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); in do_mem_zpz()
/qemu/scripts/qapi/
H A Dvisit.py44 def gen_visit_decl(name: str, scalar: bool = False) -> str:
46 if not scalar:
379 self._genh.add(gen_visit_decl(name, scalar=True))
/qemu/tests/qapi-schema/
H A Dalternate-conflict-num-string.json1 # alternate branches of 'str' type conflict with all scalar types
H A Dalternate-conflict-bool-string.json1 # alternate branches of 'str' type conflict with all scalar types
H A Dalternate-conflict-string.json1 # alternate branches of 'str' type conflict with all scalar types
/qemu/target/s390x/
H A Dcpu_features_def.h.inc332 DEF_FEAT(PCC_SCALAR_MULT_P256, "pcc-scalar-mult-p256", PCC, 64, "PCC Scalar-Multiply-P256")
333 DEF_FEAT(PCC_SCALAR_MULT_P384, "pcc-scalar-mult-p384", PCC, 65, "PCC Scalar-Multiply-P384")
334 DEF_FEAT(PCC_SCALAR_MULT_P512, "pcc-scalar-mult-p521", PCC, 66, "PCC Scalar-Multiply-P521")
335 DEF_FEAT(PCC_SCALAR_MULT_ED25519, "pcc-scalar-mult-ed25519", PCC, 72, "PCC Scalar-Multiply-Ed25519")
336 DEF_FEAT(PCC_SCALAR_MULT_ED448, "pcc-scalar-mult-ed448", PCC, 73, "PCC Scalar-Multiply-Ed448")
337 DEF_FEAT(PCC_SCALAR_MULT_X25519, "pcc-scalar-mult-x25519", PCC, 80, "PCC Scalar-Multiply-X25519")
338 DEF_FEAT(PCC_SCALAR_MULT_X448, "pcc-scalar-mult-x448", PCC, 81, "PCC Scalar-Multiply-X448")
/qemu/qapi/
H A Dstats.json137 # @scalar: single unsigned 64-bit integers.
146 'data': { 'scalar': 'uint64',
/qemu/target/hexagon/
H A Dattribs_def.h.inc47 DEF_ATTRIB(SCALAR_LOAD, "Load is scalar", "", "")
48 DEF_ATTRIB(SCALAR_STORE, "Store is scalar", "", "")
/qemu/stats/
H A Dstats-hmp-cmds.c117 monitor_printf(mon, ": %" PRId64 "\n", stats_value->u.scalar); in print_stats_results()
/qemu/backends/
H A Dcryptodev.c490 stats->value->u.scalar = *val; in cryptodev_backend_stats_add()
/qemu/target/hexagon/imported/mmvec/
H A Dext.idef1565 "Vector even halfwords with scalar lower halfword multiply with shift and sat32",
1571 "Vector even halfwords with scalar lower halfword multiply with shift and sat32",
1584 "Vector halfword with scalar halfword multiply with round, shift, and sat16",
1591 "Vector even halfword unsigned multiply by scalar",
1597 "Vector even halfword unsigned multiply by scalar",
2035 "Extract an element from a vector to scalar",
2048 ITERATOR_INSN_MPY_SLOT_LATE(32,lvsplatw, "Vd32=vsplat(Rt32)", "Replicates scalar across words in ve…
2050 ITERATOR_INSN_MPY_SLOT_LATE(16,lvsplath, "Vd32.h=vsplat(Rt32)", "Replicates scalar across halves in…
2052 ITERATOR_INSN_MPY_SLOT_LATE(8,lvsplatb, "Vd32.b=vsplat(Rt32)", "Replicates scalar across bytes in v…
2335 "Vector even halfword unsigned multiply by scalar",
[all …]
/qemu/docs/devel/
H A Dtracing.rst130 * For everything else, use primitive scalar types (char, int, long) with the
H A Dtcg-ops.rst809 - | Shift all elements from v1 by a scalar *i2*/*s2*. I.e.
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc550 /* AdvSIMD scalar shift by immediate */
558 /* AdvSIMD scalar three same */
574 /* AdvSIMD scalar two-reg misc */
/qemu/accel/kvm/
H A Dkvm-all.c3887 stats->value->u.scalar = *stats_data; in add_kvmstat_entry()
/qemu/target/i386/tcg/
H A Ddecode-new.c.inc1691 case X86_SIZE_ss: /* SSE/AVX scalar single precision */
1703 case X86_SIZE_sd: /* SSE/AVX scalar double precision */

12