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Searched refs:slot_num (Results 1 – 3 of 3) sorted by relevance

/qemu/target/hexagon/
H A Dtranslate.c641 TCGv slot = tcg_constant_tl(slot_num); in gen_check_store_width()
650 if (pkt->insn[i].slot == slot_num) { in slot_is_predicated()
658 void process_store(DisasContext *ctx, int slot_num) in process_store() argument
667 if (slot_num == 1 && ctx->s1_store_processed) { in process_store()
692 switch (ctx->store_width[slot_num]) { in process_store()
694 gen_check_store_width(ctx, slot_num); in process_store()
696 hex_store_addr[slot_num], in process_store()
700 gen_check_store_width(ctx, slot_num); in process_store()
706 gen_check_store_width(ctx, slot_num); in process_store()
712 gen_check_store_width(ctx, slot_num); in process_store()
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H A Dop_helper.c98 static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra) in commit_store() argument
100 uint8_t width = env->mem_log_stores[slot_num].width; in commit_store()
101 target_ulong va = env->mem_log_stores[slot_num].va; in commit_store()
105 cpu_stb_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra); in commit_store()
108 cpu_stw_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra); in commit_store()
111 cpu_stl_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra); in commit_store()
114 cpu_stq_data_ra(env, va, env->mem_log_stores[slot_num].data64, ra); in commit_store()
121 void HELPER(commit_store)(CPUHexagonState *env, int slot_num) in HELPER()
124 commit_store(env, slot_num, ra); in HELPER()
H A Dtranslate.h286 void process_store(DisasContext *ctx, int slot_num);