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Searched refs:tcg_target_available_regs (Results 1 – 11 of 11) sorted by relevance

/qemu/tcg/
H A Dtcg.c252 static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; variable
3399 = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); in la_reset_pref()
3518 set = tcg_target_available_regs[ts->type] & mask; in la_cross_call()
3704 tcg_target_available_regs[ts->type]; in liveness_pass_1()
3892 *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; in liveness_pass_1()
4278 temp_load(s, ts, tcg_target_available_regs[ts->type], in temp_sync()
4630 temp_load(s, ts, tcg_target_available_regs[itype], in tcg_reg_alloc_mov()
4664 oreg = tcg_reg_alloc(s, tcg_target_available_regs[otype], in tcg_reg_alloc_mov()
4917 temp_load(s, ts, tcg_target_available_regs[ts->type], in tcg_reg_alloc_op()
5020 temp_load(s, ts, tcg_target_available_regs[ts->type], in tcg_reg_alloc_op()
[all …]
/qemu/tcg/tci/
H A Dtcg-target.c.inc933 tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;
935 tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc2385 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2386 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
2401 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc3134 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
3135 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
3136 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3137 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
/qemu/tcg/sparc64/
H A Dtcg-target.c.inc1640 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
1641 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
/qemu/tcg/i386/
H A Dtcg-target.c.inc4301 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
4303 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
4306 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
4307 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
4310 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
/qemu/tcg/s390x/
H A Dtcg-target.c.inc3477 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
3478 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
3480 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3481 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
/qemu/tcg/arm/
H A Dtcg-target.c.inc2291 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2302 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2303 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
/qemu/tcg/riscv/
H A Dtcg-target.c.inc2169 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2170 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
/qemu/tcg/ppc/
H A Dtcg-target.c.inc4288 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
4289 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
4291 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
4292 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
/qemu/tcg/mips/
H A Dtcg-target.c.inc2586 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2588 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;