/qemu/tests/tcg/ppc64/ |
H A D | non_signalling_xscv.c | 8 uint64_t th, tl, bh = B_HI, bl = B_LO; \ 16 : "=r" (th), "=r" (tl) \ 20 "%016" PRIx64 "\n", bh, bl, th, tl); \ 21 assert(th == T_HI && tl == T_LO); \
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H A D | bcdsub.c | 29 uint64_t th, tl; \ 46 : "=r" (cr), "=r" (th), "=r" (tl) \ 51 assert(th == TH); \
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/qemu/target/riscv/insn_trans/ |
H A D | trans_xthead.c.inc | 111 * th.addsl shifts rs2. 157 /* th.ext and th.extu perform signed/unsigned bitfield extraction */ 183 /* th.ff0: find first zero (clz on an inverted input) */ 325 /* th.mveqz: "if (rs2 == 0) rd = rs1;" */ 332 /* th.mvnez: "if (rs2 != 0) rd = rs1;" */ 504 /* th.mula: "rd = rd + rs1 * rs2" */ 519 /* th.mulaw: "rd = sext.w(rd + rs1 * rs2)" */ 528 /* th.muls: "rd = rd - rs1 * rs2" */ 543 /* th.mulsw: "rd = sext.w(rd - rs1 * rs2)" */ 1014 * th.sync is an out-of-order barrier. [all …]
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/qemu/tests/unit/ |
H A D | test-seccomp.c | 148 pthread_t th; in doit_thread() local 149 int ret = pthread_create(&th, NULL, noop, NULL); in doit_thread() 154 pthread_join(th, NULL); in doit_thread()
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H A D | test-util-filemonitor.c | 410 QemuThread th; in test_file_monitor_events() local 443 qemu_thread_create(&th, "event-loop", in test_file_monitor_events()
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/qemu/tests/bench/ |
H A D | qht-bench.c | 247 QemuThread *th; in th_create_n() local 250 th = g_malloc(sizeof(*th) * n); in th_create_n() 251 *threads = th; in th_create_n() 259 qemu_thread_create(&th[i], name, thread_func, &info[i], in th_create_n()
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/qemu/host/include/aarch64/host/ |
H A D | store-insert-al16.h.inc | 27 uint64_t tl, th, vl, vh, ml, mh; 43 : [mem] "+Q"(*ps), [f] "=&r"(fail), [l] "=&r"(tl), [h] "=&r"(th)
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/qemu/pc-bios/keymaps/ |
H A D | meson.build | 32 'th': '-l th',
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H A D | th | 4 # layout : th
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/qemu/ui/ |
H A D | vnc-enc-zrle.c.inc | 80 int tx, th; 82 th = MIN(VNC_ZRLE_TILE_HEIGHT, y + h - ty); 90 buf = zrle_convert_fb(vs, tx, ty, tw, th, ZRLE_BPP); 91 ZRLE_ENCODE_TILE(vs, buf, tw, th, zywrle_level);
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/qemu/hw/net/ |
H A D | net_tx_pkt.c | 602 struct tcp_hdr *th; in net_tx_pkt_tcp_fragment_init() local 629 th = l4->iov_base; in net_tx_pkt_tcp_fragment_init() 630 th->th_flags &= ~(TH_FIN | TH_PUSH); in net_tx_pkt_tcp_fragment_init() 676 struct tcp_hdr *th = l4hdr->iov_base; in net_tx_pkt_tcp_fragment_advance() local 682 th->th_seq = cpu_to_be32(be32_to_cpu(th->th_seq) + fragment_len); in net_tx_pkt_tcp_fragment_advance() 683 th->th_flags &= ~TH_CWR; in net_tx_pkt_tcp_fragment_advance()
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/qemu/target/s390x/tcg/ |
H A D | translate_vx.c.inc | 1350 TCGv_i64 th = tcg_temp_new_i64(); 1355 tcg_gen_add2_i64(tl, th, th, zero, ah, zero); 1412 TCGv_i64 th = tcg_temp_new_i64(); 1417 tcg_gen_add2_i64(tl, th, tl, th, bl, zero); 1418 tcg_gen_add2_i64(tl, th, th, zero, ah, zero); 2318 tcg_gen_andi_i64(th, th, 1); 2319 tcg_gen_sub2_i64(tl, th, ah, zero, th, zero); 2320 tcg_gen_sub2_i64(tl, th, tl, th, bh, zero); 2322 tcg_gen_addi_i64(dl, th, 1); 2356 tcg_gen_not_i64(th, bh); [all …]
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/qemu/migration/ |
H A D | colo.c | 933 QemuThread th; in colo_incoming_co() local 938 qemu_thread_create(&th, "COLO incoming", colo_process_incoming_thread, in colo_incoming_co() 947 qemu_thread_join(&th); in colo_incoming_co()
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/qemu/docs/sphinx-static/ |
H A D | theme_overrides.css | 81 .rst-content table.field-list th.field-name {
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/qemu/tests/qemu-iotests/ |
H A D | 246.out | 207 --- 4th Boot (Verification and Cleanup) ---
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/qemu/tcg/riscv/ |
H A D | tcg-target.c.inc | 731 TCGReg th = TCG_REG_TMP1; 744 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh); 746 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh)); 748 th = ah; 760 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0); 779 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
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/qemu/tcg/mips/ |
H A D | tcg-target.c.inc | 830 TCGReg th = TCG_TMP1; 843 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 845 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 847 th = ah; 859 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 871 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
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/qemu/target/ppc/translate/ |
H A D | vmx-impl.c.inc | 939 TCGv_i64 th, tl, t0, t1, zero = tcg_constant_i64(0), 942 th = tcg_temp_new_i64(); 962 tcg_gen_shr_i64(th, t1, t0); 970 tcg_gen_extract2_i64(tl, tl, th, 1); 971 tcg_gen_shri_i64(th, th, 1); 974 tcg_gen_xor_i64(mh, mh, th);
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/qemu/target/arm/tcg/ |
H A D | translate.c | 4374 TCGv_i32 t0, t1, tl, th; in DO_QADDSUB() local 4397 th = load_reg(s, a->rd); in DO_QADDSUB() 4401 tcg_gen_add2_i32(tl, th, tl, th, t0, t1); in DO_QADDSUB() 4403 store_reg(s, a->rd, th); in DO_QADDSUB()
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H A D | mve_helper.c | 2166 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
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/qemu/docs/specs/ |
H A D | ppc-spapr-numa.rst | 202 distance (10), keeping it exclusive to the 4th NUMA level (which is still
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/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_vec.c.inc | 2794 TCGv_i64 rh, rl, arg1, arg2, th, tl; 2805 th = tcg_temp_new_i64(); 2814 func(tl, th, arg1, arg2); 2815 tcg_gen_add2_i64(rl, rh, rl, rh, tl, th);
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/qemu/tcg/s390x/ |
H A D | tcg-target.c.inc | 696 * is the left-shift of the 4th operand.
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/qemu/ |
H A D | qemu-options.hx | 736 da en-gb et fr fr-ch is lt nl pl ru th 3088 assign. Default is the 15th to 31st IP in the guest network, 3149 set to addr. By default the 4th IP in the guest network is used,
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/qemu/tcg/ppc/ |
H A D | tcg-target.c.inc | 3912 * So using negative numbers gets us the 4th bit easily.
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