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Searched refs:th (Results 1 – 25 of 25) sorted by relevance

/qemu/tests/tcg/ppc64/
H A Dnon_signalling_xscv.c8 uint64_t th, tl, bh = B_HI, bl = B_LO; \
16 : "=r" (th), "=r" (tl) \
20 "%016" PRIx64 "\n", bh, bl, th, tl); \
21 assert(th == T_HI && tl == T_LO); \
H A Dbcdsub.c29 uint64_t th, tl; \
46 : "=r" (cr), "=r" (th), "=r" (tl) \
51 assert(th == TH); \
/qemu/target/riscv/insn_trans/
H A Dtrans_xthead.c.inc111 * th.addsl shifts rs2.
157 /* th.ext and th.extu perform signed/unsigned bitfield extraction */
183 /* th.ff0: find first zero (clz on an inverted input) */
325 /* th.mveqz: "if (rs2 == 0) rd = rs1;" */
332 /* th.mvnez: "if (rs2 != 0) rd = rs1;" */
504 /* th.mula: "rd = rd + rs1 * rs2" */
519 /* th.mulaw: "rd = sext.w(rd + rs1 * rs2)" */
528 /* th.muls: "rd = rd - rs1 * rs2" */
543 /* th.mulsw: "rd = sext.w(rd - rs1 * rs2)" */
1014 * th.sync is an out-of-order barrier.
[all …]
/qemu/tests/unit/
H A Dtest-seccomp.c148 pthread_t th; in doit_thread() local
149 int ret = pthread_create(&th, NULL, noop, NULL); in doit_thread()
154 pthread_join(th, NULL); in doit_thread()
H A Dtest-util-filemonitor.c410 QemuThread th; in test_file_monitor_events() local
443 qemu_thread_create(&th, "event-loop", in test_file_monitor_events()
/qemu/tests/bench/
H A Dqht-bench.c247 QemuThread *th; in th_create_n() local
250 th = g_malloc(sizeof(*th) * n); in th_create_n()
251 *threads = th; in th_create_n()
259 qemu_thread_create(&th[i], name, thread_func, &info[i], in th_create_n()
/qemu/host/include/aarch64/host/
H A Dstore-insert-al16.h.inc27 uint64_t tl, th, vl, vh, ml, mh;
43 : [mem] "+Q"(*ps), [f] "=&r"(fail), [l] "=&r"(tl), [h] "=&r"(th)
/qemu/pc-bios/keymaps/
H A Dmeson.build32 'th': '-l th',
H A Dth4 # layout : th
/qemu/ui/
H A Dvnc-enc-zrle.c.inc80 int tx, th;
82 th = MIN(VNC_ZRLE_TILE_HEIGHT, y + h - ty);
90 buf = zrle_convert_fb(vs, tx, ty, tw, th, ZRLE_BPP);
91 ZRLE_ENCODE_TILE(vs, buf, tw, th, zywrle_level);
/qemu/hw/net/
H A Dnet_tx_pkt.c602 struct tcp_hdr *th; in net_tx_pkt_tcp_fragment_init() local
629 th = l4->iov_base; in net_tx_pkt_tcp_fragment_init()
630 th->th_flags &= ~(TH_FIN | TH_PUSH); in net_tx_pkt_tcp_fragment_init()
676 struct tcp_hdr *th = l4hdr->iov_base; in net_tx_pkt_tcp_fragment_advance() local
682 th->th_seq = cpu_to_be32(be32_to_cpu(th->th_seq) + fragment_len); in net_tx_pkt_tcp_fragment_advance()
683 th->th_flags &= ~TH_CWR; in net_tx_pkt_tcp_fragment_advance()
/qemu/target/s390x/tcg/
H A Dtranslate_vx.c.inc1350 TCGv_i64 th = tcg_temp_new_i64();
1355 tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
1412 TCGv_i64 th = tcg_temp_new_i64();
1417 tcg_gen_add2_i64(tl, th, tl, th, bl, zero);
1418 tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
2318 tcg_gen_andi_i64(th, th, 1);
2319 tcg_gen_sub2_i64(tl, th, ah, zero, th, zero);
2320 tcg_gen_sub2_i64(tl, th, tl, th, bh, zero);
2322 tcg_gen_addi_i64(dl, th, 1);
2356 tcg_gen_not_i64(th, bh);
[all …]
/qemu/migration/
H A Dcolo.c933 QemuThread th; in colo_incoming_co() local
938 qemu_thread_create(&th, "COLO incoming", colo_process_incoming_thread, in colo_incoming_co()
947 qemu_thread_join(&th); in colo_incoming_co()
/qemu/docs/sphinx-static/
H A Dtheme_overrides.css81 .rst-content table.field-list th.field-name {
/qemu/tests/qemu-iotests/
H A D246.out207 --- 4th Boot (Verification and Cleanup) ---
/qemu/tcg/riscv/
H A Dtcg-target.c.inc731 TCGReg th = TCG_REG_TMP1;
744 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh);
746 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
748 th = ah;
760 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0);
779 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
/qemu/tcg/mips/
H A Dtcg-target.c.inc830 TCGReg th = TCG_TMP1;
843 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
845 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
847 th = ah;
859 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
871 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc939 TCGv_i64 th, tl, t0, t1, zero = tcg_constant_i64(0),
942 th = tcg_temp_new_i64();
962 tcg_gen_shr_i64(th, t1, t0);
970 tcg_gen_extract2_i64(tl, tl, th, 1);
971 tcg_gen_shri_i64(th, th, 1);
974 tcg_gen_xor_i64(mh, mh, th);
/qemu/target/arm/tcg/
H A Dtranslate.c4374 TCGv_i32 t0, t1, tl, th; in DO_QADDSUB() local
4397 th = load_reg(s, a->rd); in DO_QADDSUB()
4401 tcg_gen_add2_i32(tl, th, tl, th, t0, t1); in DO_QADDSUB()
4403 store_reg(s, a->rd, th); in DO_QADDSUB()
H A Dmve_helper.c2166 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
/qemu/docs/specs/
H A Dppc-spapr-numa.rst202 distance (10), keeping it exclusive to the 4th NUMA level (which is still
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_vec.c.inc2794 TCGv_i64 rh, rl, arg1, arg2, th, tl;
2805 th = tcg_temp_new_i64();
2814 func(tl, th, arg1, arg2);
2815 tcg_gen_add2_i64(rl, rh, rl, rh, tl, th);
/qemu/tcg/s390x/
H A Dtcg-target.c.inc696 * is the left-shift of the 4th operand.
/qemu/
H A Dqemu-options.hx736 da en-gb et fr fr-ch is lt nl pl ru th
3088 assign. Default is the 15th to 31st IP in the guest network,
3149 set to addr. By default the 4th IP in the guest network is used,
/qemu/tcg/ppc/
H A Dtcg-target.c.inc3912 * So using negative numbers gets us the 4th bit easily.