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Searched refs:tlb (Results 1 – 25 of 64) sorted by relevance

123

/qemu/target/ppc/
H A Dmmu_helper.c52 tlb = &env->tlb.tlb6[nr]; in ppc6xx_tlb_invalidate_all()
70 tlb = &env->tlb.tlb6[nr]; in ppc6xx_tlb_invalidate_virt2()
97 tlb = &env->tlb.tlb6[nr]; in ppc6xx_tlb_store()
117 tlb = &env->tlb.tlbe[i]; in ppc4xx_tlb_invalidate_all()
691 tlb = &env->tlb.tlbe[entry]; in helper_4xx_tlbre_hi()
711 tlb = &env->tlb.tlbe[entry]; in helper_4xx_tlbre_lo()
750 tlb = &env->tlb.tlbe[entry]; in helper_4xx_tlbwe_hi()
785 (int)entry, tlb->RPN, tlb->EPN, tlb->size, in helper_4xx_tlbwe_hi()
801 tlb = &env->tlb.tlbe[entry]; in helper_4xx_tlbwe_lo()
821 (int)entry, tlb->RPN, tlb->EPN, tlb->size, in helper_4xx_tlbwe_lo()
[all …]
H A Dmmu-booke.c42 mask, (uint32_t)tlb->PID, tlb->prot); in ppcemb_tlb_check()
44 if (tlb->PID != 0 && tlb->PID != pid) { in ppcemb_tlb_check()
58 ppcemb_tlb_t *tlb; in ppcemb_tlb_search() local
63 tlb = &env->tlb.tlbe[i]; in ppcemb_tlb_search()
75 ppcemb_tlb_t *tlb; in mmu40x_get_physical_address() local
81 tlb = &env->tlb.tlbe[i]; in mmu40x_get_physical_address()
192 ppcemb_tlb_t *tlb; in mmubooke_get_physical_address() local
196 tlb = &env->tlb.tlbe[i]; in mmubooke_get_physical_address()
240 __func__, address, pid, tlb->mas1, tlb->mas2, mask, in ppcmas_tlb_check()
241 tlb->mas7_3, tlb->mas8); in ppcmas_tlb_check()
[all …]
H A Dmmu_common.c92 ppc6xx_tlb_t *tlb; in ppc6xx_tlb_check() local
103 tlb = &env->tlb.tlb6[nr]; in ppc6xx_tlb_check()
110 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); in ppc6xx_tlb_check()
117 tlb->EPN, eaddr, tlb->pte1, in ppc6xx_tlb_check()
121 if (!pte_is_valid(tlb->pte0) || ((tlb->pte0 >> 6) & 1) != 0 || in ppc6xx_tlb_check()
134 *raddr = tlb->pte1; in ppc6xx_tlb_check()
368 entry = &env->tlb.tlbe[0]; in mmubooke_dump_mmu()
407 entry = &env->tlb.tlbm[offset]; in mmubooke206_dump_one_tlb()
503 ppc6xx_tlb_t *tlb; in mmu6xx_dump_mmu() local
538 tlb = &env->tlb.tlb6[entry]; in mmu6xx_dump_mmu()
[all …]
H A Dmmu-booke.h10 hwaddr booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb);
11 int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp,
/qemu/target/mips/tcg/sysemu/
H A Dtlb_helper.c55 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_fill_tlb()
94 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_helper_tlbinv()
127 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_helper_tlbwi()
183 tlb = &env->tlb->mmu.r4k.tlb[i]; in r4k_helper_tlbp()
202 tlb = &env->tlb->mmu.r4k.tlb[i]; in r4k_helper_tlbp()
243 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_helper_tlbr()
259 env->CP0_EntryHi = mi ? tlb->VPN : tlb->VPN | tlb->ASID; in r4k_helper_tlbr()
319 tlb = &env->tlb->mmu.r4k.tlb[idx]; in global_invalidate_tlb()
403 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; in r4k_map_address() local
1371 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_invalidate_tlb()
[all …]
/qemu/target/loongarch/tcg/
H A Dtlb_helper.c120 LoongArchTLB *tlb = &env->tlb[index]; in invalidate_tlb_entry() local
154 tlb = &env->tlb[index]; in invalidate_tlb()
165 LoongArchTLB *tlb = &env->tlb[index]; in fill_tlb_entry() local
200 tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1); in fill_tlb_entry()
243 tlb = &env->tlb[index]; in helper_tlbrd()
335 tlb = &env->tlb[i * 256 + (index % 256)]; in helper_tlbclr()
345 tlb = &env->tlb[i]; in helper_tlbclr()
393 LoongArchTLB *tlb = &env->tlb[i]; in helper_invtlb_all_g() local
408 LoongArchTLB *tlb = &env->tlb[i]; in helper_invtlb_all_asid() local
425 LoongArchTLB *tlb = &env->tlb[i]; in helper_invtlb_page_asid() local
[all …]
/qemu/target/sh4/
H A Dmonitor.c30 static void print_tlb(Monitor *mon, int idx, tlb_t *tlb) in print_tlb() argument
37 tlb->asid, tlb->vpn, tlb->ppn, tlb->sz, tlb->size, in print_tlb()
38 tlb->v, tlb->sh, tlb->c, tlb->pr, in print_tlb()
39 tlb->d, tlb->wt); in print_tlb()
/qemu/target/loongarch/
H A Dcpu_helper.c19 LoongArchTLB *tlb = &env->tlb[index]; in loongarch_map_tlb_entry() local
25 tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); in loongarch_map_tlb_entry()
31 tlb_entry = n ? tlb->tlb_entry1 : tlb->tlb_entry0; in loongarch_map_tlb_entry()
94 LoongArchTLB *tlb; in loongarch_tlb_search() local
108 tlb = &env->tlb[i * 256 + stlb_idx]; in loongarch_tlb_search()
109 tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); in loongarch_tlb_search()
113 tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G); in loongarch_tlb_search()
125 tlb = &env->tlb[i]; in loongarch_tlb_search()
126 tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); in loongarch_tlb_search()
129 tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); in loongarch_tlb_search()
[all …]
/qemu/hw/ppc/
H A Dppc440_bamboo.c118 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; in mmubooke_create_initial_mapping() local
120 tlb->attr = 0; in mmubooke_create_initial_mapping()
122 tlb->size = 1U << 31; /* up to 0x80000000 */ in mmubooke_create_initial_mapping()
123 tlb->EPN = va & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
124 tlb->RPN = pa & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
125 tlb->PID = 0; in mmubooke_create_initial_mapping()
127 tlb = &env->tlb.tlbe[1]; in mmubooke_create_initial_mapping()
128 tlb->attr = 0; in mmubooke_create_initial_mapping()
131 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
132 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
[all …]
H A Dvirtex_ml507.c75 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; in mmubooke_create_initial_mapping() local
77 tlb->attr = 0; in mmubooke_create_initial_mapping()
79 tlb->size = 1U << 31; /* up to 0x80000000 */ in mmubooke_create_initial_mapping()
80 tlb->EPN = va & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
81 tlb->RPN = pa & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
82 tlb->PID = 0; in mmubooke_create_initial_mapping()
84 tlb = &env->tlb.tlbe[1]; in mmubooke_create_initial_mapping()
85 tlb->attr = 0; in mmubooke_create_initial_mapping()
88 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
89 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
[all …]
H A Dsam460ex.c219 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; in mmubooke_create_initial_mapping_uboot() local
225 tlb->attr = 0; in mmubooke_create_initial_mapping_uboot()
227 tlb->size = 0x10000000; /* up to 0xffffffff */ in mmubooke_create_initial_mapping_uboot()
228 tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping_uboot()
230 tlb->PID = 0; in mmubooke_create_initial_mapping_uboot()
238 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; in mmubooke_create_initial_mapping() local
240 tlb->attr = 0; in mmubooke_create_initial_mapping()
242 tlb->size = 1 << 31; /* up to 0x80000000 */ in mmubooke_create_initial_mapping()
243 tlb->EPN = va & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
244 tlb->RPN = pa & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
[all …]
H A Dppce500_spin.c78 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1); in mmubooke_create_initial_mapping() local
82 tlb->mas1 = MAS1_VALID | size; in mmubooke_create_initial_mapping()
83 tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M; in mmubooke_create_initial_mapping()
84 tlb->mas7_3 = pa & TARGET_PAGE_MASK; in mmubooke_create_initial_mapping()
85 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; in mmubooke_create_initial_mapping()
/qemu/target/openrisc/
H A Dsys_helper.c102 mr = env->tlb.dtlb[idx].mr; in HELPER()
109 env->tlb.dtlb[idx].mr = rb; in HELPER()
113 env->tlb.dtlb[idx].tr = rb; in HELPER()
125 mr = env->tlb.itlb[idx].mr; in HELPER()
132 env->tlb.itlb[idx].mr = rb; in HELPER()
136 env->tlb.itlb[idx].tr = rb; in HELPER()
300 return env->tlb.dtlb[idx].mr; in HELPER()
304 return env->tlb.dtlb[idx].tr; in HELPER()
316 return env->tlb.itlb[idx].mr; in HELPER()
320 return env->tlb.itlb[idx].tr; in HELPER()
H A Dmmu.c41 uint32_t imr = cpu->env.tlb.itlb[idx].mr; in get_phys_mmu()
42 uint32_t itr = cpu->env.tlb.itlb[idx].tr; in get_phys_mmu()
43 uint32_t dmr = cpu->env.tlb.dtlb[idx].mr; in get_phys_mmu()
44 uint32_t dtr = cpu->env.tlb.dtlb[idx].tr; in get_phys_mmu()
/qemu/qga/vss-win32/
H A Dmeson.build27 gen_tlb = custom_target('gen-tlb',
29 output: 'qga-vss.tlb',
30 command: [midl, '@INPUT@', '/tlb', '@OUTPUT@'])
32 gen_tlb = custom_target('gen-tlb',
34 output: 'qga-vss.tlb',
H A Dqga-vss.idl11 importlib("stdole2.tlb");
/qemu/accel/tcg/
H A Dcputlb.c334 qemu_spin_init(&cpu->neg.tlb.c.lock); in tlb_init()
337 cpu->neg.tlb.c.dirty = 0; in tlb_init()
340 tlb_mmu_init(&cpu->neg.tlb.d[i], &cpu->neg.tlb.f[i], now); in tlb_init()
387 qemu_spin_lock(&cpu->neg.tlb.c.lock); in tlb_flush_by_mmuidx_async_work()
389 all_dirty = cpu->neg.tlb.c.dirty; in tlb_flush_by_mmuidx_async_work()
392 cpu->neg.tlb.c.dirty = all_dirty; in tlb_flush_by_mmuidx_async_work()
1041 CPUTLB *tlb = &cpu->neg.tlb; in tlb_set_page_full() local
1132 qemu_spin_lock(&tlb->c.lock); in tlb_set_page_full()
1135 tlb->c.dirty |= 1 << mmu_idx; in tlb_set_page_full()
1197 qemu_spin_unlock(&tlb->c.lock); in tlb_set_page_full()
[all …]
H A Dmonitor.c135 full += qatomic_read(&cpu->neg.tlb.c.full_flush_count); in tlb_flush_counts()
136 part += qatomic_read(&cpu->neg.tlb.c.part_flush_count); in tlb_flush_counts()
137 elide += qatomic_read(&cpu->neg.tlb.c.elide_flush_count); in tlb_flush_counts()
/qemu/target/sparc/
H A Dldst_helper.c122 static void replace_tlb_entry(SparcTLBEntry *tlb, in replace_tlb_entry() argument
129 if (TTE_IS_VALID(tlb->tte)) { in replace_tlb_entry()
135 va = tlb->tag & mask; in replace_tlb_entry()
142 tlb->tag = tlb_tag; in replace_tlb_entry()
143 tlb->tte = tlb_tte; in replace_tlb_entry()
172 if (TTE_IS_VALID(tlb[i].tte)) { in demap_tlb()
176 if (TTE_IS_GLOBAL(tlb[i].tte) || in demap_tlb()
239 uint32_t ctx = tlb[i].tag & 0x1fffU; in replace_tlb_1bit_lru()
256 if (!TTE_IS_VALID(tlb[i].tte)) { in replace_tlb_1bit_lru()
273 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) { in replace_tlb_1bit_lru()
[all …]
H A Dmmu_helper.c484 static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, in ultrasparc_tag_match() argument
488 uint64_t mask = -(8192ULL << 3 * TTE_PGSIZE(tlb->tte)); in ultrasparc_tag_match()
491 if (TTE_IS_VALID(tlb->tte) && in ultrasparc_tag_match()
492 (TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context)) in ultrasparc_tag_match()
493 && compare_masked(address, tlb->tag, mask)) { in ultrasparc_tag_match()
495 *physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL; in ultrasparc_tag_match()
/qemu/target/hppa/
H A Dmachine.c115 memset(env->tlb, 0, sizeof(env->tlb)); in tlb_pre_load()
135 for (uint32_t i = 0; i < ARRAY_SIZE(env->tlb); ++i) { in tlb_post_load()
136 HPPATLBEntry *e = &env->tlb[i]; in tlb_post_load()
156 VMSTATE_ARRAY(tlb, CPUHPPAState,
157 ARRAY_SIZE(((CPUHPPAState *)0)->tlb),
H A Dmem_helper.c104 is_btlb = ent < &env->tlb[HPPA_BTLB_ENTRIES(env)]; in hppa_flush_tlb_ent()
143 if (i < btlb_entries || i >= ARRAY_SIZE(env->tlb)) { in hppa_alloc_tlb_ent()
148 ent = &env->tlb[i]; in hppa_alloc_tlb_ent()
635 memset(&env->tlb[btlb_entries], 0, in hppa_ptlbe()
636 sizeof(env->tlb) - btlb_entries * sizeof(env->tlb[0])); in hppa_ptlbe()
641 env->tlb_unused = &env->tlb[btlb_entries]; in hppa_ptlbe()
643 env->tlb[i].unused_next = &env->tlb[i + 1]; in hppa_ptlbe()
649 if (env->tlb[i].entry_valid) { in hppa_ptlbe()
748 btlb = &env->tlb[slot]; in HELPER()
770 btlb = &env->tlb[slot]; in HELPER()
[all …]
/qemu/target/mips/sysemu/
H A Dphysaddr.c92 return env->tlb->map_address(env, physical, prot, real_address, in get_seg_physical_address()
149 ret = env->tlb->map_address(env, physical, prot, in get_physical_address()
158 ret = env->tlb->map_address(env, physical, prot, in get_physical_address()
199 ret = env->tlb->map_address(env, physical, prot, in get_physical_address()
/qemu/hw/pci-host/
H A Dpnv_phb3.c740 IOMMUTLBEntry *tlb) in pnv_phb3_translate_tve() argument
769 tlb->iova = addr & 0xfffffffffffff000ull; in pnv_phb3_translate_tve()
770 tlb->translated_addr = addr & 0x0003fffffffff000ull; in pnv_phb3_translate_tve()
771 tlb->addr_mask = 0xfffull; in pnv_phb3_translate_tve()
772 tlb->perm = IOMMU_RW; in pnv_phb3_translate_tve()
831 tlb->iova = addr & tce_mask; in pnv_phb3_translate_tve()
832 tlb->translated_addr = tce & tce_mask; in pnv_phb3_translate_tve()
833 tlb->addr_mask = ~tce_mask; in pnv_phb3_translate_tve()
834 tlb->perm = tce & 3; in pnv_phb3_translate_tve()
/qemu/target/xtensa/
H A Dmmu_helper.c250 const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb; in xtensa_tlb_get_entry() local
252 assert(wi < tlb->nways && ei < tlb->way_size[wi]); in xtensa_tlb_get_entry()
334 const xtensa_tlb *tlb, in reset_tlb_mmu_all_ways() argument
339 for (wi = 0; wi < tlb->nways; ++wi) { in reset_tlb_mmu_all_ways()
340 for (ei = 0; ei < tlb->way_size[wi]; ++ei) { in reset_tlb_mmu_all_ways()
348 const xtensa_tlb *tlb, in reset_tlb_mmu_ways56() argument
351 if (!tlb->varway56) { in reset_tlb_mmu_ways56()
463 const xtensa_tlb *tlb = dtlb ? in xtensa_tlb_lookup() local
471 for (wi = 0; wi < tlb->nways; ++wi) { in xtensa_tlb_lookup()

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