Searched refs:tlb_debug (Results 1 – 1 of 1) sorted by relevance
| /qemu/accel/tcg/ |
| H A D | cputlb.c | 67 #define tlb_debug(fmt, ...) do { \ macro
385 tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked); in tlb_flush_by_mmuidx_async_work()
419 tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap); in tlb_flush_by_mmuidx()
435 tlb_debug("mmu_idx: 0x%"PRIx16"\n", idxmap); in tlb_flush_by_mmuidx_all_cpus_synced()
517 tlb_debug("forcing full flush midx %d (%016" in tlb_flush_page_locked()
546 tlb_debug("page addr: %016" VADDR_PRIx " mmu_map:0x%x\n", addr, idxmap); in tlb_flush_page_by_mmuidx_async_0()
610 tlb_debug("addr: %016" VADDR_PRIx " mmu_idx:%" PRIx16 "\n", addr, idxmap); in tlb_flush_page_by_mmuidx()
629 tlb_debug("addr: %016" VADDR_PRIx " mmu_idx:%"PRIx16"\n", addr, idxmap); in tlb_flush_page_by_mmuidx_all_cpus_synced()
690 tlb_debug("forcing full flush midx %d (" in tlb_flush_range_locked()
703 tlb_debug("forcing full flush midx %d (" in tlb_flush_range_locked()
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