/qemu/target/rx/ |
H A D | op_helper.c | 202 uint8_t tmp0, tmp1; in helper_scmpu() local 207 tmp0 = cpu_ldub_data_ra(env, env->regs[1]++, GETPC()); in helper_scmpu() 210 if (tmp0 != tmp1 || tmp0 == '\0') { in helper_scmpu() 214 env->psw_z = tmp0 - tmp1; in helper_scmpu() 215 env->psw_c = (tmp0 >= tmp1); in helper_scmpu() 328 int64_t tmp0, tmp1; in helper_rmpa() local 340 tmp0 = cpu_ldfn[sz](env, env->regs[1], GETPC()); in helper_rmpa() 342 tmp0 *= tmp1; in helper_rmpa() 344 result_l += tmp0; in helper_rmpa() 346 if (tmp0 < 0) { in helper_rmpa()
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H A D | translate.c | 1702 TCGv_i64 tmp0, tmp1; in rx_mul64hi() local 1703 tmp0 = tcg_temp_new_i64(); in rx_mul64hi() 1705 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); in rx_mul64hi() 1706 tcg_gen_sari_i64(tmp0, tmp0, 16); in rx_mul64hi() 1709 tcg_gen_mul_i64(ret, tmp0, tmp1); in rx_mul64hi() 1715 TCGv_i64 tmp0, tmp1; in rx_mul64lo() local 1716 tmp0 = tcg_temp_new_i64(); in rx_mul64lo() 1718 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); in rx_mul64lo() 1719 tcg_gen_ext16s_i64(tmp0, tmp0); in rx_mul64lo() 1722 tcg_gen_mul_i64(ret, tmp0, tmp1); in rx_mul64lo()
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/qemu/target/i386/tcg/ |
H A D | translate.c | 136 TCGv tmp0; member 1519 tcg_gen_shr_i64(s->tmp0, s->T0, s->tmp0); in gen_shiftd_rm_T1() 1523 tcg_gen_shl_i64(s->tmp0, s->T0, s->tmp0); in gen_shiftd_rm_T1() 1525 tcg_gen_shri_i64(s->tmp0, s->tmp0, 32); in gen_shiftd_rm_T1() 1533 tcg_gen_shr_tl(s->tmp0, s->T0, s->tmp0); in gen_shiftd_rm_T1() 1539 tcg_gen_shl_tl(s->tmp0, s->T0, s->tmp0); in gen_shiftd_rm_T1() 1544 tcg_gen_or_tl(s->tmp0, s->tmp0, s->tmp4); in gen_shiftd_rm_T1() 3321 tcg_gen_shli_tl(s->tmp0, s->tmp0, ot); in disas_insn_old() 3333 tcg_gen_shl_tl(s->tmp0, s->tmp0, s->T1); in disas_insn_old() 3346 tcg_gen_not_tl(s->tmp0, s->tmp0); in disas_insn_old() [all …]
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H A D | emit.c.inc | 1141 carry_in = s->tmp0; 1466 tcg_gen_xor_tl(s->tmp0, s->cc_srcT, cmpv); 1467 tcg_gen_and_tl(s->tmp0, s->tmp0, newv); 1468 tcg_gen_sextract_tl(s->tmp0, s->tmp0, 0, 8 << ot); 1469 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(0); 1473 tcg_gen_ext8u_tl(s->tmp0, s->T0); 1474 tcg_gen_ctpop_tl(s->tmp0, s->tmp0); 1475 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(1); 1479 tcg_gen_sextract_tl(s->tmp0, s->T0, 0, 8 << ot); 1480 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(0);
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/qemu/target/mips/tcg/ |
H A D | op_helper.c | 56 uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff); in helper_rotx() local 57 uint64_t tmp1 = tmp0; in helper_rotx() 70 if (tmp0 & (1LL << (i + 16))) { in helper_rotx()
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/qemu/target/loongarch/tcg/ |
H A D | tlb_helper.c | 555 target_ulong phys, tmp0, ptindex, ptoffset0, ptoffset1, ps, badv; in helper_ldpte() local 592 tmp0 = base; in helper_ldpte() 594 tmp0 += MAKE_64BIT_MASK(ps, 1); in helper_ldpte() 608 tmp0 = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK; in helper_ldpte() 613 env->CSR_TLBRELO1 = tmp0; in helper_ldpte() 615 env->CSR_TLBRELO0 = tmp0; in helper_ldpte()
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/qemu/hw/s390x/ |
H A D | css.c | 780 CCW0 tmp0; in copy_ccw_from_guest() local 791 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0)); in copy_ccw_from_guest() 792 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) { in copy_ccw_from_guest() 797 ret.cmd_code = tmp0.cmd_code; in copy_ccw_from_guest() 798 ret.flags = tmp0.flags; in copy_ccw_from_guest() 799 ret.count = be16_to_cpu(tmp0.count); in copy_ccw_from_guest() 801 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16); in copy_ccw_from_guest()
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/qemu/target/ppc/translate/ |
H A D | vmx-impl.c.inc | 2824 tmp0 = tcg_temp_new_i64(); 2833 get_avr64(tmp0, a->vra, false); 2835 tcg_gen_mulu2_i64(prod1l, prod1h, tmp0, tmp1); 2838 get_avr64(tmp0, a->vra, true); 2840 tcg_gen_mulu2_i64(prod0l, prod0h, tmp0, tmp1); 2844 tcg_gen_add2_i64(tmp1, tmp0, tmp1, zero, prod1l, zero); 2845 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0l, zero); 2852 tcg_gen_add2_i64(tmp1, tmp0, tmp0, zero, tmp1, zero); 2853 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod1h, zero); 2854 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0h, zero); [all …]
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/qemu/target/hexagon/idef-parser/ |
H A D | README.rst | 641 add_i32 tmp0,r2,r2 642 mov_i32 loc2,tmp0 646 Here we have finally located our bug ``add_i32 tmp0,r2,r2``.
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/qemu/tcg/mips/ |
H A D | tcg-target.c.inc | 699 /* ret and arg can't be register tmp0 */
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/qemu/tcg/aarch64/ |
H A D | tcg-target.c.inc | 1772 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {tmp0,tmp1}. */
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