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Searched refs:ttr (Results 1 – 5 of 5) sorted by relevance

/qemu/target/m68k/
H A Dmonitor.c51 { "dttr0", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR0]) },
52 { "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]) },
53 { "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]) },
54 { "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]) },
H A Dhelper.c580 static void dump_ttr(uint32_t ttr) in dump_ttr() argument
582 if ((ttr & M68K_TTR_ENABLED) == 0) { in dump_ttr()
589 switch (ttr & M68K_TTR_SFIELD) { in dump_ttr()
600 DUMP_CACHEFLAGS(ttr); in dump_ttr()
601 if (ttr & M68K_DESC_WRITEPROT) { in dump_ttr()
666 dump_ttr(env->mmu.ttr[M68K_ITTR0]); in dump_mmu()
668 dump_ttr(env->mmu.ttr[M68K_ITTR1]); in dump_mmu()
670 dump_ttr(env->mmu.ttr[M68K_DTTR0]); in dump_mmu()
672 dump_ttr(env->mmu.ttr[M68K_DTTR1]); in dump_mmu()
692 switch (ttr & M68K_TTR_SFIELD) { in check_TTR()
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H A Dcpu.h77 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
138 uint32_t ttr[4]; member
H A Dcpu.c466 VMSTATE_UINT32_ARRAY(env.mmu.ttr, M68kCPU, 4),
H A Dtranslate.c6198 env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1], in m68k_cpu_dump_state()
6199 env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]); in m68k_cpu_dump_state()